EMULATION OF THE AN/UYK-7
TACTICAL DATA COMPUTER ON THE
BURROUGHS D-MACHINE
Jerry Michael Haggerty
"""mm***
NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
EMULATION OF THE AN/UYK-7
TACTICAL DATA COMPUTER ON THE
BURROUGH'S D-MACHINE
by
Jerry Michael Haggerty
and
John Michael Hartling
December 1976
Thesis Advisor: S. Jauregui
Approved for public release; distribution unlimited.
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Emulation of the AN/UYK-7 Tactical
Data Computer on the Burrough's
D-Machine
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Master's Thesis;
December 1976
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Jerry Michael Haggerty and
John Michael Hartling
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Naval Postgraduate School
Monterey, CA 9 3940
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19. KEY WOROS (Contlnum on rmwmroo m!4o if nmcmmmmrr mnm laontlfy by block nummort
emulation
AN/UYK-7
interpreter
microprogramming
20. ABSTRACT (Contlnuo on rmvmrmm olttm If nocooomr mnd Identify by •/•«* iw bor)
A workable design is presented for emulating the AN/UYK-7
multiprocessing computer system on the Burrough's Interpreter
Based System, the D-Machine. The program developed provides
for exact execution of the AN/UYK-7 instruction repertoire with
the exception of Floating Point, hardware interrupts and IOC
Instructions. The design allows for future expansion to
incorporate these functions. Input/Output is limited to a card
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reader, line printer and single disk. Various aspects of
Emulation, the D-Machine, and the AN/UYK-7 are discussed
and a detailed User's Manual is provided along with recom-
mendations for modifying the design into a full emulation.
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2
Emu 1 at i on
of the
AN/UYK-7
Tactical Data Comouter
On the
Burrough's D-Machine
by
Jerry Michael Haggerty
Lieutenant f United States Navy
B.S., United States Naval Academy, 1970
John Michael Hartling
Lieutenant, United States Navy
B.S., Miami University, Oxford, Ohio, 1969
Submitted in partial fulfillment of the
requirements for the degree of
MASTER OF SCIENCE IN COMPUTER SCIENCE
f rom the
NAVAL POSTGRADUATE SCHOOL
DECEMBER 1976
«VAL POSTGRADUATE SCHOOL
ABSTRACT
A workable design is presented for emulat ina the
AN/UYK-7 multiprocessing computer system on the Burrough's
Interoreter Based System/ the D-Machine. The program
developed provides for exact execution of the AN/UYK-7
instruction repertoire with the exception of Floating Point/
hardware interrupts and IOC Instructions. The design allows
for future expansion to incorporate these functions.
Input/Output is limited to a card reader/ line printer and
single disk. Various asoects of Emulation/ the D-Machine/
and the AN/UYK-7 are discussed and a detailed User's Manual
is provided along with recommendations for modifying the
design into a full emulation.
CONTENTS
ACKNOWLEDGEMENTS 8
I. INTRODUCTION 9
II. EMULATION 12
A. GENERAL CONCEPTS OF MICROPROGRAMMING 13
B. BUILDING AN EMULATOR 17
C. APPLICATIONS 24
III. THE AN/UYK-7 27
A. INTERRUPTS 28
B. CENTRAL PROCESSOR 29
1. Program Address Reqister (PAR) 30
2. Active Status Register (ASR) 31
3. Base Register (S) 32
4. Arithmetic Reaister (A) 32
5. Index Register (B) 32
C. INSTRUCTION FORMAT 3a
D. MODES OF OPERATION 37
IV. BURROUGH'S D-MACHINE 38
A. GENERAL DESCRIPTION 38
1. Logic Unit (LU) 38
2. Memory Control Unit (MCU) 42
3. Control Unit (CU) ^3
4. Microprogram ( ^-Memory ).......... 44
B. NAVAL POSTGRADUATE SCHOOL CONFIGURATION 47
1. Desc r i ot i on . . 47
3. I/O Interface 49
3. Memory Interface 49
C. INSTRUCTION TIMING 50
D. LANGUAGES 51
1. ALGOL 51
2. TRANSLANG 5?
V. PROJECT DESCRIPTION 54
A. LOADER 56
8. EMULATION PROGRAM 57
C. REGISTER MAPPING 67
D. TIMING 69
VI. SUMMARY 71
A. PROBLEMS 71
8. CONCLUSIONS 73
VII. RECOMMENDATIONS 75
APPENDIX A. USER'S MANUAL 78
APPENDIX 8. EMULATOR PROGRAM LISTING 91
APPENDIX C. LOADER PROGRAM LISTING 139
APPENDIX D. SAMPLE AN/UYK-7 SORT PROGRAM 154
APPENDIX t. SAMPLE LOADER OUTPUT LISTING 157
APPENDIX F. SAMPLE DEBUGGER OUTPUT LISTING 161
GLOSSARY 167
6
BIBLIOGRAPHY 175
INITIAL DISTRIBUTION 178
ACKNOWLEDGEMENTS
We would like to take this opportunity to express our
sincere appreciation to the following people for the support
they have provided us over the last six months during our
pursuit of this thesis. To Professor S. Jauregui* first
for sponsoring the thesis* and second for providing funds
for research trips to PaoH # Pa. and San Diego* Ca.
without w h. i c h the project could not have been done. To Mr.
J. Lynch* Burrough's Advanced Development Organization
(ADO)* for providing software and hardware engineers on
three occasions* and whose personnel graciously answered our
guestions during almost daily phone calls. To Mr. Carl Ben-
son* Naval Electronics Systems Engineering Center (NESEO*
San Diego* for his financial support and personal interest
in the project. And last but not least our wives ana fami-
lies who had the patience to see us through this thesis in
spite of our 1M hour days away from home* and who soothed
our frayed nerves when things did not go right.
I. INTRODUCTION
In its effort to provide the Fleet with officers well
versed in all aspects of Computer Sciencef the Naval Post-
graduate School strives to furnish each student in the Com-
puter Science Curriculum with ample opportunities for
hands-on operation and programming exDerience on a variety
of computer systems. The systems presently available for
this puroose include the IBM 360/67, POP 11/45, XOS 9300,
and several varieties of microcomputers and stand alone
graphic systems. Unfortunately, this wide range of avail-
able systems and their incorporated programming languages
does not include any of the numerous tactical computer sys-
tems in use in the Fleet today? moreover, because of
budgetary and procurement lead time constraints, it is
highly unlikely that the school will have such a system in
the near future. To provide the desired systems, the Chief
of Naval Education and Training and the Naval Postgraduate
School* with the assistance of Burrough's Corporation, have
provided a medium through which students may gain experience
and perform research on, not one or two Tactical Data Sys-
tems but potentially on any particular computer in which the
student may express an interest. This medium is the
Burrouqh's Interpreter Based System, a microprogrammable
computer, hereafter referred to as the Burrough's D-Machine.
Through microproqramming, the D-Machine can be made to
operate exactly like any designated computer of interest.
Through the process of Emulation the authors sought to
demonstrate that the D-Machine could be microprogrammed to
imitate a selected computer. As the target computer, the
authors selected the AN/UYK-7 which is used extensively in
Tactical Data Systems and is one of the more complex systems
in use today. It was felt that if a realistic emulation of
the AN/UYK-7 could be demonstrated* then any lower level »
less sophisticated computer could also be successfully emu-
1 ated.
The goal of this thesis was not a complete AN/UYK-7
emulation* but rather development of the design for the Emu-
lation* and adoption of a sufficient subset of the AN/UYK-7
instruction repertoire to demonstrate exact and efficient
execution of AN/UYK-7 programs. The oesign allows for a
complete emulation of all AN/UYK-7 functions and provides
for future expansion to a complete emulation including all
IOC Functions. Chapters II* III and IV are designed to
provide the reader with a general knowledge of Emulation*
the AN/UYK-7 and the Burrough's D-Machine. Chapter V
describes the methods used for imitating the AN/UYK-7
instructions and its various modes of operation. Chapter V
also defines the maooing of the AN/UYK-7 Control Memory
Registers and status bits into the Burrough's D-Machine for
the purpose of this Emulation. Chapter VI presents some of
the problems encountered in the course of this thesis* and
10
the conclusions drawn by the authors as a result of this
Emulation, ChaDter VII orovides recommendations for expand-
ing this Emulation and suggests possible follow on thesis
topics. Appendix A is included as a User's Manual » and con-
tains information on how to use the D-Machine, how to run
AN/UYK-7 programs on the Emulator/ and how to use special
features of the microprogramming language TRANSLANG which
were not documented in the TRANSLANG Programmer's Manual.
The program listings of the Loader and Emulator/ written in
association with this thesis and used to demonstrate the
feasibility of the design by running AN/UYK-7 Programs/ are
included as Appendix B and C. A sort routine written in
AN/UYK-7 machine language/ and used to demonstrate the
Emulator's capability is orovided in Apoendix D. The output
of the sort program and the optional Loader functions of
assembler and debugger are presented as Appendix E and F.
11
II. EMULATION
Modern computer systems are generally composed of five
basic units: input* outout* memory* ar i t hme t i c/ 1 ogi c * and
control. The instruction execution and communications among
these units are usually well understood with the exception
of the control unit which is* typically* understood only by
the system engineer. The control unit generates the signals
necessary for the information flow and timing of the system.
In conventional computers this is done through the use of
flip-flops (e.g. registers and counters) and gates designed
in a relatively ad hoc manner. Microprogramming the control
unit has been proposed as an orderly alternative to this ad
hoc design procedure where the hardware of the control sec-
tion is replaced by a "microprogram control" unit.
Microprogramming is therefore a technique for imple-
menting the control function of a digital computer using
programmable control signals stored in a separate* word-
organized memory* called control store. If the control
store were a programmable memory* then the system architec-
ture could be modified to optimize processing of each task
to be performed; moreover* it could be altered completely to
resemble the architecture of another* entirely different
machine. The microprogramming of the control store of a
computer system to alter the basic architecture enablina one
12
machine (the host machine) to execute machine language pro-
grams intended for another machine (the target machine) is
defined as Emulation.
The remainder of this chanter is divided into three
sections: general information on microprogramming, construc-
tion of an emulator and applications of emulation.
A. GENERAL CONCEPTS OF MICROPROGRAMMING
Since the cost of software has become a major portion of
the overall cost of comouter systems today, more and more
manufacturers and users are turning to microprogramming the
control section of their computer to tailor the machine to
individual app 1 i cat i ons , thereby making computer programming
more efficient.
The main function of the control section is to specify
the conditions under which sets of gates are to be opened.
In conventional machines this can lead to a very complex,
hardwired system, especially if the instruction set is
extensive. A relatively simple field change* addition or
alteration, may reguire a major modification of this complex
system. This is not true in a computer that uses a
mi c roprogrammab 1 e control store. The complex hardwired
structure is replaced by microinstructions stored in the
control store, one microinstruction per word, which tell the
system which arithmetic and loaic ooerations to perform by
specifying which gates to enable/disable. In this way,
13
control of the comouter is removed from the hardware and
placed under the control of the microprogrammer. This
places a heavy burden on the programmer since he must become
intimately familiar with the innermost workings of the
machine/ however/ it allows him to m oci el the machine to his
specific programming needs. This gives the microorogrammer
extreme flexibility in his aoplications on the computer.
There are two types of microinstructions: vertical and
horizontal. Vertical microinstructions usually control one
operation; and the address of the successor microinstruction
is implicitly the current address plus one/ unless the
current microooeration causes a branch. In horizontally mi-
croprogrammed machines each control bit of a microinstruc-
tion is assignee to a specific gate or set of gates. This
means that one microinstruction can control multiple opera-
tions. On the other hand/ vertical microinstructions are
divided into separate fields/ each of which are then decoded
to enable/disable specific qates or sets of gates? there-
fore/ horizontal microinstructions reauire less decoding and
provide more flexibility. However/ the advantage of verti-
cal microinstructions is that they generally reguire shorter
control words considerably reducing the overall cost of con-
trol micromemory. The length of control words vary from 20
bits (vertical) to in excess of 120 bits (horizontal); the
average microinstruction is 50-80 bits. The D-Machine/ the
host machine for this thesis/ utilizes a combination of
14
vertical (Type II) and horizontal (Tyoe I) microinstructions
in the form of a 56-bit word.
Since the execution time of one horizontal microinstruc-
tion is essentially the same as that of one vertical mi-
croinstruction/ the multiple operations performed during one
horizontal instruction is a desirable feature. This paral-
lelism can drastically reduce the size of a microprogram,
and dramatically decrease execution times. These reductions
can only be realized* however* if the programmer can recog-
nize concurrent actions and optimally group them into one
instruction. A great deal of work has been done toward in-
cluding the efficient use of available resources into a com-
piler for a high-level m i c roorogrammi ng language* but with
little success. Either the probability of making the deter-
mination is low* or the cost of the optimization is too
high. Much additional research is requirea in the area of
recognizing and combining potentially concurrent actions.
Different m i c ro i nt rue t i ons specify different microopera-
tions to be performed* and deoending on the nature of the
mi c rooperat i ons * some phase of one instruction may overlap a
phase of a subsequent instruction. Instruction timing is*
therefore* an imoortant factor in the overall efficiency of
microprograms in which m i c rooperat i ons are not mutually ex-
clusive. A brief description of the timing considerations
that must be made in microprogramming the Burrough's D-
Machine is given in Chapter IV.
15
Many main-frame manufacturers hesitate to allow the no-
vice programmer access to the innermost workings of their
computer (e.g. registers/ data oaths/ and gates). One
method of prohibiting this access is to use read-only m i -
cromemory with the microprograms being provided by the com-
puter manufacturer. This helps preserve the designed iden-
tity of the computer out does not provide for its optimum
use. The programmer who is given the capability of modify-
ing the logical design of the machine to his specific pro-
gramming needs will find his programming tasks greatly sim-
plified. For example* he could implement new instructions*
such as floating point* which were not designed into the
original mach i ne .
In summary* microprogramming is becoming more widely
used for the following reasons: 1) the flexibility and
growth potential of mi c roprogrammab 1 e machines (especially
in the area of emulation)* 2) increasing software costs and
current semi-conductor technology favor microprogram design*
and 3) user-or i en t ec instructions can be designed into
machines through microprogramming.
16
B. BUILDING AN EMULATOR
Emulation describes a orocess through which the hardware
components of one machine (host) are made to "appear" to as-
sume the soecific characteristics of the hardware of another
machine (target). This provides the host machine with the
capability of executing machine language instructions
written for the target machine. Simulation is a software
process that provides the same capability for program
execution? however* simulation involves interpretive
execution Dy a high-level language program. Emulation
differs in that an emulator performs its interpretive execu-
tion through the hardware. Simulations usually perform
within a factor of 100-200 times real-time. Emulation is
generally within a factor of 10, but often can be tuned to
approach real-time. For this reason emulations are usually
more cost-effective than simulations. The following oara-
graphs describe the process involved in building an emula-
tor.
There are two major aporoaches to emulating a target
machine: 1) the hardware and firmware (the physical realiza-
tion of a microprogram) can be used in conjunction with a
software simulator (software alone would be pure simula-
tion)/ or 2) the hardware and firmware can execute with no
software suooort .
Depending on trie percentage of software utilized/ a
software-assisted emulation may be somewhat slower than a
17
firmware emulation. Typically/ the programmer mentally
develops a software simulation of the target machine. He
then decides which sequences of instructions are most fre-
quently used, and which are the hardest to simulate. These
become candidates for microprogramming. Frequently a single
new instruction can be microprogrammed to replace repetitive
sequences of the same high-level instructions, thus speeding
up the emulation. With this software-firmware approach the
user must decide the point at which he must stop substitut-
ing microcode for software routines. This is generally
dependent on the amount of control storage available* or the
cos t -per f ormance criteria with which he is working. An ex-
ample of a software-hardware approach to emulation is the
IBM 7000 series emulators used with the IBM System/360 Model
65.
The Burrough's D-Machine provides the capability of emu-
lation using the software-hardware method. A simulation is
written in the high-level language ALGOL. ALGOL on the D-
Machine allows the user to define a new operator which, when
called in the simulation program, branchs to a preprogrammed
series of microinstructions; executes the microinstructions;
and returns to the ALGOL program. This gives the user the
ability to execute frequently used routines (such as in-
struction fetch) from micromemory which has a faster cycle
time than that of main memory where the ALGOL simulator re-
sides. An advantaqe to this approach is that the system
does not have to oe regenerated after different emulators
18
are run since* in essence* only an ALGOL program has been
executed. However* as previously discussed* this software
emulator is slower than a firmware-controlled emulator.
The authors used the hardware-firmware approach in their
emulation of the AN/IJYK-7. This method will be developed in
more detail along with suggested hardware additions which
could enhance the emulation. Control of the system resides
entirely in the firmware* which means that the emulator*
once loaded* dedicates the machine to that emulation* and
native mode programs can no longer execute until system re-
generation. This unproductive overhead of loading and re-
loading the emulator and the native mode machine is one
drawback. An additional drawback is the larger micromemory
required since the entire emulation is microprogrammed.
However* the emulator executes exclusively through firmware
making this approach to emulation significantly faster. An
example of a firmware-controlled emulator is the IBM 1401
emulator on the System/360 Model 30.
Although systems such as the D-Machine use horizontal
microinstructions to enable oarallel or concurrent opera-
tions* the microprogram can only perform one function of the
target machine at a time. That is* if the target machine
performs parallel operations such as executing one instruc-
tion while simultaneously fetching the next instruction* the
microprogram can only emulate one of these functions at a
time. It must execute the current instruction and then
fetch the next instruction. For this reason* emulation is
19
usually slower than the real time performance of the target
machine even though it may have a faster memory cycle time.
In order to emulate a target machine* the microprogram-
mer must first understand three areas: 1) the host machine*
2) the target machine and 3) the m i c ro 1 anguage . Second* the
registers* counters* and accumulators of the target machine
must be mapped into the host machine. This is often done in
two steps - depending on the number of available registers
in the host machine. The registers of the target machine
most freguently used should be mapped directly to registers
in the host where possible. The remaining registers of the
emulated machine are mapped into the host's main memory. As
many of the target machine's registers as possible should be
mapped directly* so that fewer memory references will be re-
quired Dy the emulator. For example* if the emulator were
executing a Load Accumulator instruction and the specified
accumulator had been mapped into one of the host's regis-
ters* then only one microinstruction is needed to emulate
the load instruction. However* if the accumulator had been
mapped to a memory location* then it would take several mi-
croinstructions to emulate the entire operation - i.e. setup
the store address* store the value to be loaded into the
write register* and perform a write to main memory. Not
only does this require additional instructions* but it also
includes a main memory access* whose cycle time is slower
than m i c romemory ' s cycle time. Some instructions may re-
quire two main memory cycles* such as an ADD where the
20
maDped accumulator must be read, added to and then written
out. This demonstrates the necessity of mapping as many
registers as oossible to the host machine's hardware. Sel-
dom, however* can this mapping be accomplished without some
use of main memory? therefore* the m i c roprogrammer must
select some portion of main memory as a privileged area for
reaister mapping. The authors reserved the first 1024 words
of main memory in the emulation of the AN/UYK-7, for regis-
ter and buffer mapping.
The next step in the emulation is to assume that a
user's object program is resident in main memory. The emu-
lator must then fetch, decode and execute the program, in-
struction by instruction. The m i c roprogrammer must decide
which emulation functions should be written as subroutines,
and which functions should be written in line. The most fre-
quently referenced subroutine in any emulation is the fetch
routine since it is executed for every instruction. The
normal steos involved in this routine arel
1. Determine the address of the next instruction
as indicated by the program address reaister.
2. Read the instruction from the main memory ad-
dress calculated in step 1. This is the
current instruction to be emulated.
3. Decode the instruction into its designator
fields.
a. Calculate the operand address. (The AN/UYK-7
uses a displacement plus an index register plus
a base register).
5. Read the ooerand fro1"" main memory.
21
6. Perform indirection if allowed and indicated.
7. Some instruction sets, AN/UYK-7 for example,
allow whole or half-words. Check if current
instruction is half-word.
8. Some instruction sets ooerate on partial word
operands. If so determine if quarter, half or
full-word operand is to be used.
These steps must be executeo for each instruction
fetched from the user's program. Depending on the particu-
lar instruction beinq emulated, some of these steps may be
omitted (step 8 is only performed for Format I instructions)
but the majority are generally apolicable. This demon-
strates the overhead involved in emulation prior to branch-
ing to the microroutine that does the actual instruction ex-
ecut i on .
Some hardware additions that can facilitate emulation
are a fast shifter and a field select unit (FSU). The
shifter simplifies va r i ab 1 e-1 enqt h byte extraction, a common
emulation process. For instance, in the D-Machine it takes
the same amount of time to shift a word by 1 bit as it does
for any shift uo to 31 Oits. The FSU allows the testing of
selected fields without requiring a cycle to go through the
adder (the O-Machine does not have this feature). This re-
lieves the programmer of masking and shifting fields prior
to testing them. These two features are the most common and
cost-effective additions to the hardware.
22
One approach to emulation that has recently come into
use; but which is not that widely usea or understood/ in-
volves using a combination of hardware/ software and operat-
ing system. IBM js experimenting in this area, and has es-
tablished the following design characteristics for the Sys-
tem/370 emulators:
1. Emulators must be integrated with the operating
system and run as a problem program. This el-
iminates the overhead of loading and reloading
the emulator and the native mode machines.
2 . Allow multiprogramming of emulators as well as
a mix of emulators and native mode programs.
3. All programs including emulators must be inter-
rupt i b 1 e.
With such a system IBM felt they could give the user an
improved/ more efficient environment from which to operate/
either in the emulator or native mode. The authors feel
this should be a primary field for future applications.
The final item to be discussed in the Section is emula-
tion of Inout/Output operations. Most sources agree that
emulation of I/O is as difficult/ if not more so/ than the
implementation of the central processor's instruction set.
This is true primarily because once the basic routines need-
ed for instruction and operand fetch are programmed/ the ac-
tual instruction executions are fairly easy to microprogram.
This is not necessarily true with I/O - buffers must be set
up/ data conversion possibly performed/ ana perhaps the
hardest Doint/ emulating circumstances in which results are
23
not yet known. For instance/ if the I/O is to search for a
specified record/ then what happens if the key cannot be
found? There are many such checks or error conditions that
make I/O difficult to emulate. Another major problem is
emulating interrupt handling during I/O. Since emulation of
I/O is essentially a separate topic and since the authors
did not implement emulation of the AN/UYK-7 Input/Output in-
struction set as part of the thesis* I/O emulation will not
be descrioed in any further detail. However/ references 5/
12/ 15/ 21/ and 22 provide excellent material on this topic.
C. APPLICATIONS
This section is designed to familiarize the reader with
some of the apolicable areas for emulation usage. It is by
no means an exhaustive study of this topic/ nor is it in-
tended to be so.
Emulation was first used in/ and is still the primary
application for/ converting from second generation computing
systems to third generation systems. Normally/ the process
is costly and danqerous in the aspect of converting programs
running on the existinq system to programs capable of exe-
cuting on the new machine. There are several methods other
than emulation capable of performing this task/ none of
which are completely satisfactory: simulation is slow; au-
tomated translation is unproven; and instruction by instruc-
tion reorogramm i ng is costly and cumbersome. The advantaoe
of emulation is that if the old machine could be emulated on
24
the new machine allowing direct execution of all old pro-
grams* then the old Drograms could be converted at leisure?
if desired and justified. For example? reprogramming might
not be cost effective or justified for a program with an ex-
pected life span of six months. In such circumstances con-
tinued emulation of the program is the solution. However?
the situation might be different if the program had an ex-
pected life span of three years.
Another major application for emulation is the design?
development? and testing of a newly conceived system on an
existing system. The target machine does not necessarily
have to be an existing computer system? and the user could
experiment with the design of any machine he desires. In
this way a richer instruction set can be achieved? moreover?
software and diagnostic routines could be developed for the
new machine prior to the machine even being produced or
marketed. IBM used this method to some extent by emulating
System/370 on System/360 prior to building System/370. This
application tends to decrease the time from initial con-
struction to marketing because software? such as the operat-
ing system? can be tested and debugged concurrently.
A third application? and one seen as a major trend for
the future? is the ability of the user to adapt the computer
to his individual neeas. Modern-day computers are built as
powerful? general-ourpose machines designed to operate
effectively over a large field of problems. In doing so?
however? the machine cannot optimize execution of any one
25
particular application. Emulation gives the user this
ability. The user can either operate from an existing
emulator, or he can tune the emulator to his individual
application through microprogramming. One user may want a
machine oriented toward string operations, while another
user mav be doing extensive scientific calculations. If
each user could execute from a separate emulator tuned to
his individual application, then each would be more
efficient and productive. In addition the computer would
orobably be easier for the user to program. This is the
area where mu 1 t i programmi na of emulators is projected to be
of the most use .
There are several other areas of emulation usage which
were not discussed? such as the academic environment for
research purooses (the reason for this thesis), and tuning
of existing software. However, as previously stated, this
section was designed only to give the reader a flavor of the
possible uses of emulation and perhaps stimulate his own
ideas for oossible applications. For additional and more
detailed material see references 2, 15 through 18, and 20
through 24.
26
III. THE AN/UYK-7
This chapter is intended to introduce the reader to
those operational characteristics and capabilites of the
AN/UYK-7 computer most pertinent to the Emulation. This
will assist the reader in understanding the design and map-
pings used in this Emulation, and presented in subsequent
chapters. This chapter is not intended to be a technical
manual and should not be used for that ourpose. The reader
should consult references 26 and 27 for more detailed infor-
mation.
The AN/UYK-7 is a highly reliable, ruggedized, mul-
tiprocessor system designed and manufactured by the Univac
Division of Soerry Rand Corporation. Built to military
specifications (MIL-E-16400) , it is utilized extensively
throughout the United States Navv in Tactical Data Process-
ing aoplications [2b). Rapid data transfer rates are pro-
vided during communications between external devices , inter-
nal random-access memory, and the central processor. The
system is capable of average command execution times of 1.5
microseconds, and an input data transfer rate of over one
million 32-bit words oer second. The AN/UYK-7 maintains two
completely separate sets of index, arithmetic and relative
address (Base) registers, for use during Task and Executive
states. In addition, a set of 18 privileged instructions
27
with special characteristics for executive control are
reserved for the Interruot State. These features alonq with
the parallelism of AN/UYK-7 field and register references,
make it an extremely difficult system to emulate in real-
time.
The AN/UYK-7 was desiqned to operate as either a single
or multiple processor system with up to 256K, 32-bit words
of random access memory. This allows on-line access to
1024K bytes through an instruction feature which permits
whole-word, half-word/ or quarter-word memory references.
This Emulation assumed an AN/UYK-7 configuration consisting
of a single processor, monoorogramm i ng, with one t>4K, 32-bit
word memory module. Partial word references were fully emu-
lated providing random access to 256K bytes.
A. INTERRUPTS
The AN/UYK-7 processes data in real-time in response to
a highly prioritized interrupt system with decision-making
properties. This oriority system allows the central pro-
cessor to select that program routine which is necessary to
respond to the interrupt reguiring the most urgent atten-
tion. Since the Emulator was designed for a monoprogramming
environment using asynchronous I/O, the interrupt features
of the AN/UYK-7 were not fully implemented. Several types
of interrupts, such as Program Faults (Illegal Instruc-
tions), were implemented and tested. All interrupt handling
flags, lockouts and registers were maooed into the Emulator.
28
This will facilitate full implementation of interrupt
features - should a decision be made to incorporate mul-
tiprogramminq or synchronous I/O in the course of expansion
to a full Emu 1 at i on .
B. CENTRAL PROCESSOR
The AN/UYK-7 central processor contains all the control >
arithmetic and timing circuitry required for processing al-
Dhanumeric data and for executive functions. The central
processor operates in two different modes or states: the In-
terrupt State executes execut i ve-t yDe functions* and the
Task State processes user programs. A grouo of 16
privileged instructions and a separate set of arithmetic*
index and base registers are reserved for the exclusive use
of the processor while in the Interrupt State. These
features greatly enhance the AN/UYK-7's multiprocessing and
multiprogramming capabilities. These special instructions
and registers were mapped into the Emulator; however* they
were not fully implemented because of the monoprogramming
environment in which the Emulator was to be run.
The AN/UYK-7 maintains a central processor control
memory (CMR) consisting of 82 i nt egrat ed-c i rcu i t * random-
access registers of varying sizes appropriate to their func-
tion (e.g. A-registers 32-bits* B-registers 20-bits). The
various registers are grouoed into stacks according to their
use* addressing* and relative size. In the Emulator* these
registers were maooed into the D-MacMne's main memory
29
starting at address 0000, with address assignments
corresoondi ng exactly to that of the AN/UYK-7. The notable
exception was that OR addresses designated as "Unassigned"
in the AN/UYK-7 were used as temporary storage registers in
the Emulator, Register mapping is discussed in more detail
in Chapter V and presented in tabular form in Figure V-2.
The AN/UYK-7 registers of particular interest to the
user are: the Program Address Register (PAR); the Active
Status Register (ASR); and the Base, Index and Arithmetic
Register groups. These are the only registers which are ei-
ther airectly addressable or accessible to the programmer.
1. Program Address Register (PAR)
The PAR is a 20-bit register used for addressing the
next instruction to be fetched from memory for execution.
It consists of a 16-oit di sol acement value and a 3-bit Base
Register reference. The effective instruction address is
formed Dy the addition of the displacement and the contents
of the selected Base register. The PAR displacement value
is incremented by one word at the completion of each in-
struction cycle with the exception of JU^P instructions.
These instructions cause reolacement of the PAR by the Ms"
and "y" operand fielas of the JUMP, thus providing for out-
of-seguence instruction execution. The PAR mapping in the
Emulator is not composed of two separate fields* but rather
as the calculated effective address. This greatly simpli-
fies and expedites instruction references; however* it
30
causes some difficulty with specific instructions which re-
quire access to the two separate fields of the PAR. When
encountered/ this problem was overcome by dividing the PAR
value by 8K. Since the Base registers were preinitialized
in 8K increments^ starting at 1024, the results of the divi-
sion yielded a auotient eguivalent to the Base reaister as-
signment/ and a remainder equal to the displacement.
2. Active Status Register (ASR)
The ASR is a 23-bit register used to indicate and
control the status of various ooerations in the central pro-
cessor. Individual bits of the register are assigned spe-
cial functions, and when set indicate that a particular
status exists and that the processor should be controlled
accordingly. Individual bits are set/cleared as the result
of either an instruction execution or direct processor in-
tervention. The bits of particular interest to the program-
mer are the arithmetic bits (equal/ greater than or equal/
overflow/ and limits) which are set as the result of arith-
metic functions/ and may be interrogated Py specific in-
structions/ such as conditional jumps. Based on the con-
dition of the bit tested these conditional instructions may
cause a change in the program sequence. In the Emulator the
ASR bits most freauently referenced by the programmer are
mapped into a D-Machine internal register together with the
PAR. This considerably reduces main memory references/ and
reduces Emulator execution time. The ASR mapoing is dis-
cussed in oetail in Chaoter V.
31
3. Base Register (S)
There are two sets (Interrupt* Task) of 18-bit S-
Registers* numbered 0-7. These registers* used in final Y-
Operand and instruction address calculations* are necessary
in a multiprogramming and mu 1 t i Drocess i ng environment. In
spite of the monoprogr ammm i ng environment of the Emulator*
the registers were mapped and used as designed* however*
they were ©reinitialized by the Loader at 8K boundaries
starting at address 1Q2U. This provided the Emulator access
to 64K of main memory in increments of 8K Dages.
tf • Arithmetic Register* (A)
There are two sets (Interrruot* Task) of 32-bit A-
Registers* numbered 0-7. They are used extensively
throughout the instruction set to hold one or more of the
ODerand - inputs to* or results of arithmetic functions.
The A-Registers also serve as the main interface between the
central processor and main memory. These registers are
directly addressable by the programmer.
5. Index Register (B)
There are two sets (Interrupt* Task) of 20-bit B-
Registers* numbered 1-7. These registers can be used as
counters* or they can be employed in a special addressing
techniaue called Indexing. During normal Y-Operand address
calculations* the designated B-Register is added to the y-
displacement and a specific S-Register to form an effective
32
address. This address is then considered to have been in-
dexed by the B-Register value. Indexing provides the pro-
grammer with the option of seguentially referencing memory
by merely incrementing the index during each pass through a
loop. Reference to any B-Register other than B(0) implies
that indexing is to take place during the Y-Operand address
calculation. A reference to B(0) is treated as an index of
zero since 8(0) is not a valid register. In the Emulator,
the contents of B(0) is always zero , and references to B(0)
are conveniently treated the same as references to B(l) thru
B(7). In the AN/UYK-7, the 8-Registers have the same inter-
nal structure as the PAR; that is, they consist of two
fields (a Base register, and a displacement). In the Emula-
tor, B-Registers are treated as consisting of one field
which can be separatea into its two respective fields by
division by 8K, as previously described in the PAR discus-
sion.
In order to minimize access time and field decoding,
all CVR registers were treated as 32-bit registers in the
Emulator. This caused no oroblems with the exception of the
PAR and Index Registers, which were resolved as previously
discussed. The A, S, and B-Registers are directly address-
able through the Load/Store CMR Instructions of the AN/UYK-
7. They are incidentally addressable through references in
specific fields of the different Format instructions
reserved for that purpose.
33
C. INSTRUCTION FORMAT
Instructions of the central processor appear in five
different formats according to their operational charac-
teristics/ as presented in Figure III-l. Formats If 11/ and
III occupy a full/ 32-bit computer word? Formats IV-A and
IV-B each occupy a half computer word. Two half-word in-
structions can be stored in one memory location. to hen a
half-word instruction in the uoper half of the computer word
is executed/ the processor sets bit 15 of the ASR; if a
whole-word or lower half-word is executed the bit is
cleared. In the Emulator* this bit determines whether the
subroutine IFETCH or HALFFETCH is executed. IFETCH reads
the next 32-bit instruction from memory. HALFFETCH shifts
the lower half-word of the current instruction into the
upper halfword position for execution.
Each of the five formats divide the instruction into
different fields. Each field except "y" (the constant or
address field) has a particular function in controlling the
various internal enables and commands required for proDer
execution of the instruction. Some fields define the use/
modification or application of the y-field to secure the
desired operand; others select an accumulator/ index/ or
base register; others select an IOC/ define a sub-function
code/ or combine to form a special interpretation defined by
the instruction. The AN/UYK-7 maintains a repertoire of 132
central processor instructions whose specific functions are
defined in detail in reference 26.
3a
Bit No.
FORMAT I
FORMAT II
FORMAT III
Bit No.
Bit No.
FORMAT IV A
FORMAT IV 8
31--26
25-23
22-20
19-17
16
15-13
12 0
f
a
k
b
s
y
f
a
f2
b
s
V
f
i
a
f 3/k
b
s
y
31--26
15—10
25-23
9-7
22-20
6-a
19-17
3-1
16
0
f
a
fa
b
i
f
a
m
INDIRECT CONTROL WORD FORMATS (Indirect Addressing)
Bit No.
31-30
29-
25
2a-20
19-17
16
15-13
12---0
c
w
p
b
i
s
y
c
cl
unused
b
i
d
Elements of the word are interpretea as follows:
FIELD BASIC DEFINITION
t i o n code
unc t i on code
unc t i on code
unc t i on code
mulator register designator
and interpretation designator
t count designator
x register designator
rect addressing designator
des i gnat or
ess di sol acement /operand designator
ro 1 des i gnat or
rect subfunction designator
acter length designator
tion indicator for character length
ess displacement
f
6-bi t
f unc
f2
3-bi t
subf
f3
2-bi t
subf
fa
3-bi t
sub f
a
3-bi t
accu
k
3-bi t
ooer
m
6-bi t
shi f
b
3-bi t
i nde
i
1-bit
i ndi
s
3-bi t
base
y
13-bit
addr
c
2-bi t
cont
cl
1-bit
i ndi
w
6-bi t
char
p
5-bi t
oos i
d
16-bi t
addr
INSTRUCTION AND INDIRECT ADDRESS WORD FORMATS [27]
FIGURE III-l
35
Of particular note to the reaaer is the K-Field of the
Format I instructions. The value of K Designates whether
the operand to be fetched/stored is a whole* half, or
quarter-word operand/ as depicted in Figure III-2. If the
value of K implies a partial-word operation, then it also
determines which portion of the 32-bit word is to be ac-
cessea. That is, a K-value designating a auarter-word
(byte) transfer can also specify that the byte is located in
the upDer, lower, or one of the intermediate two bytes of
the 4-byte, 32-bit operand. It is this function that makes
the AN/UYK-7 an extremely powerful word processing machine.
This function was fully implemented and tested in the Emula-
tor.
READ
MEMORY to ARITHMETIC
sy(SE)+B(b) -> A15-0CSE)
Y15-0 -> A15-0 (SE)
Y31-16 -> A15-0 (SE)
Y31-0 -> A31-0
Y7-0 -> A7-0 (ZE)
Y15-8 -> A7-0 (ZE)
Y23-16 -> A7-0 (ZE)
Y31-24 -> A7-0 (ZE)
STORE
ARITHMETIC to MEMORY
NOT USED
A15-0 -> Y15-0,* Y31-16 unchg
A15-0 -> Y31-16; Y 15-0 unchg
A31-0 -> Y31-0
-> Y7-0;Y3l-8 unchg
-> Y 15-8; Y31-16 unchg
Y7-0 unchg
-> Y23-l6;Y31-2a unchg
Y15-0 unchg
-> Y31-24; Y23-0 unchg
A7-0
A 7-0
A7-0
A7-0
SE--sign extended; ZE--zero extended
A is the ACCUMULATOR specified by the a-field
FORMAT I INSTRUCTION K-FIELD INTERPRETATION [27]
FIGURE 1 1 1-2
36
D. MODES OF OPERATION
There are several different modes of operation of the
AN/UYK-7; most of them are concerned with different address-
ing techniques. Specifically, they are: normal mode* index
mode, repeat mode, and indirection. In the normal mode, the
Y-Operand address is calculated as the sum of: the y-offset,
a case register and an index register, or Y=y+B (b ) +S ( s ) .
There are two exceptions to this general formula. First, if
the K-field of Format I instructions is a zero then
Y=sy+B(b), where "sy" is the concatenation of the s-field
and y-field of the instruction. Second, for all instruc-
tions regardless of Format, if the B-field is' zero then the
B(b) value used in calculating the Y-Operand aadress is al-
ways zero. There are several additional addressing tech-
niques employed during the repeat and indirect modes of
operation. They are described in detail in Chapter V.
These ad hoc addressing techniques employed by the AN/UYK-7
greatly enhance its caoabilities but were extremely diffi-
cult functions to emulate.
37
IV. BURROUGH'S D-MACHINE
A. GENERAL DESCRIPTION
An Interpreter Based System is a digital processing con-
cept developed by Burrough's Corporation/ that utilizes
hardware building blocks which can be tailored through mi-
croprogramming to perform as a variety of general purpose op
special ourpose general processors 17/ 8» 24]. The basic
Interpreter^ also referred to as the D-^achine/ is the pri-
mary building block of this uniaue system. It is composed
of five functional modules each of which can be modified to
manipulate an 8 to 64-bit word format in increments of 8
bits. In the Naval Postgraduate School configuration, two
of these modules/ the Nanomemory and the Micromemory/ are
combined into one. The register sizes given in the follow-
ing descriptions of the modules are specific to this confi-
guration which is a 32-bit O-Machine.
1. Logic Unit (LU)
The Logic Unit (LU)/ presented in Figure IV-1/ con-
tains all the registers/ the Barrel Switch and the Adder
which are available to the m i c roorogrammer for manipulating
data fields during the process of emulating an instruction.
A description of each of these registers and its functions
fol lows [8/24] .
38
,— AMPCR
F rof Memo ry
Control Unit (MCU)
L Inputs
CTR/ZEXT/LIT
LOGIC
UNIT (LU)
Al
A2
A3
±_fc
Hi
B *
B SELECT
AOOER
BARREL SWITCH
MIR
Data Output
to Memor i es
and
Peripheral Devices
Data Input
f rom
Memor i es
and
Peripheral
Devices
+ T0 Control Unit (CU)
Dynamic Conditions
AOV/ABT/MST/LST
_^To Memory
Control Unit (MCU)
LIT/CTR/AMPCR
BR1/BR2/MAR/SAR
LOGIC UNIT (LU) BLOCK DIAGRAM
FIGURE I V-l
39
The 32-bit registers Al, A2, and A3 are functionally
identical. They temporarily store data within the Inter-
preter and serve as the primary (X) input to the adder. Any
A-Register can be designated as a destination for the output
from the Barrel Switch.
The 32-bit B-Register is the primary external input
interface (from the Switch Interlock). It also serves as
the secondary (Y) input to the Adder/ and can receive the
output of the Adder/ in addition to the Barrel Switch which
is the normal source for the results of arithmetic calcula-
tions. The B-Register can be the destination of any of the
following during execution of any one microinstruction:
a. The Barrel Switch output.
b. The Adder output.
c. The external data from the Switch
Interlock.
d. The Memory Information Register (MIR).
e. The carry complements of four-bit or
eight -bit groups.
f. The Barrel Switch output ORed with b/
c / o r d above .
The output of the B-Register has true/complement
selection gates which are controlled in three separate sec-
tions: the most significant bit (MSB)/ the least significant
bit (LSB)/ and all the remaining internal bits. Each of
these oarts is controlled independently/ and may be either
all one's/ all zero's/ the true contents or the one's com-
plement of the respective bits of the B-Register.
ao
The 32-bit Memory Information Register (MIR) buffers
the information which is to be written to main system S-
Memory, or to a peripheral device. It is loaded from the
Barrel Switch output and its output is directed either to
the Switch Interlock or the B-Register.
The 32-bit Adder in the LU is a modified version of
a straightforward carry look-ahead adder. Inputs to the
Adder are from selection gates which allow various combina-
tions of the A, S, and Z inputs. The A input is from the
A-Register output selection aates and the 8 input is from
the B-Register true/complement selection gates. The Z input
is an external input to the LU and can be:
a. The outout of the counter in the Memory Con-
trol Unit (MCU) into the most significant
eight bits with all other bits being zeros.
b. The output of the literal register in the
MCU into the least significant eight bits
with all other bits being zeros.
C. An optional input into the middle bits with
the most and least significant bytes being
zeros .
d. All zeros .
There are always two inputs to the Adder referred to
as the X-input and Y-input. An X-input may have A, 1, or
zero as its source. A Y-input may have 8, Z, or one as its
source. An unspecified X-input is always assumed to be
zero. Using various combinations of the possible inputs to
the selection gates, any two of the three (A, 8, or Z) in-
puts can be added together, or can be added together with an
41
additional one added to the least significant bit. In addi-
tion, all binary Boolean operations can be performed between
any t wo i nput s .
The 32-bit Barrel Switch is a matrix of gates that
shifts a parallel input data word from the Adder* any number
of places to the left or right/ either end-off or end-
around. The output of the Barrel Switch may be gated to one
or more of the following simultaneously:
a. The A-Registers (Al, A2, A3),
b . The B-Regi st er .
c. Memory Information Register (MIR).
d. Least significant 16 bits of MCU registers
(BR1, BR2, MAR, AMPCR, CTR).
e. Least significant 5 bits to the Control
Unit (CU) for the shift amount register
(SAR).
2. Memory Control Unit (MCU)
One MCU is required for an Interpreter to have ac-
cess to 64K of main memory [8, 241. The addition of a second
MCU is possible, thus expandinq on-line memory access to
128K. The MCU has three major sections:
a. The microprogram address section contains a
microprogram count register (MPCR), the
12-bit alternate microprogram count regis-
ter (AMPCR), the incrementer, the micropro-
gram address controls register, and their
associated control logic. This section is
used to address the Microprogram Memory
(MPM) for the seauencing of microinstruc-
tions. The AMPCR contents may be used as a
Y-inout to the Adder.
a2
b. The memory/device address section contains
the 8-bit memory address register (MAR),
the two 16-bit base registers BR1 and BR2,
the output selection gates/ and their asso-
ciated control logic.
c. The Z register section contains registers
which are the Z inputs to the LU Adder: a
loadable counter (CTR), the literal regis-
ter (LIT), selection gates for the loadable
counter and their associated control logic.
3. Control Unit (CU)
The Control Unit (CU) has five major sections: the
shift amount register (SAR), the condition register (COND),
part of the control register (CR), the MPM content decoder
and the clock control [8, 24].
The functions of the SAR and its associated logic
are :
a .
b.
To load shift amounts into the SAR for
in (0 to 32-bit) shifting operations.
use
To generate the required controls for the
Barrel Switch to perform the shift opera-
tion indicated by the current microinstruc-
tion.
To generate the "word length complement" of
the SAR contents* where the "complement" is
defined as the amount that will restore the
bits of a word to their original position
after an end-around shift of N followed by
an end-around shift by the " complement " of
N.
43
The control register (CR) is a 56-bit register that
stores all those control signals from the current microin-
struction which are not used in phase I. The CR is divided
into the phase III controls and the MPAD controls.
The condition register (COND) section of the CU per-
forms four major functions:
a. Stores 12 resettable condition bits in the
condition register. The 12 bits of the
condition register are used as interrupts*
error indicators, status indicators, and
lockout indicators.
b. Selects 1 of 16 condition bits; 12 from the
condition register and <4 dynamically gen-
erated during the present clock time in the
Logic Unit for use in oerforming condition-
a 1 operat ions.
C. Decodes bits from memory for resetting,
setting or requesting the setting of cer-
tain bits in the condition register.
d. Resolves oriority among Interpreters in the
setting of global condition (GC) bits which
provide a facility for inter-Interpreter
1 oc kout cont rol .
4. Microprogram (M-Memory)
The Micromemory (M-Memory), also known as the
Nanomemory (N -Memory) in the Naval Postgraduate School con-
figuration, is a programmable control store memory which
contains the user suoDlied microprograms in the form of mi-
croinstructions. Each microinstruction consists of a 56-bit
nanoi nst ruct i on and provides the gating for functioning of
the previously discussed LU , MCU, and CU modules. Mi-
cromemory consists of two 4K , 56-bit, modules allowing the
aa
programmer access to approximately 8K of control store. The
sequencing of microprogram instructions is controlled by the
following procedure: the Nanomemory provides information to
the condition testing logic indicating which condition is to
be tested. The condition testing logic provides a
TRUE/FALSE signal to the successor logic which selects
between the three TRUE and three FALSE successor bits.
These three successor bits provide eight possible successor
command combinations which are listed below with their asso-
ciated interpretations:
a. WAIT
b. STEP
c. SKIP
d. JUMP
e. RETN
f. CALL
g. SAVE
h. EXEC
Repeat the current instruction
Step to the next Instruction
Skip the next instruction
Jump to address in AMPCR
Return from a micro subroutine
Call a micro subroutine
Save the address of the head of
a 1 oop .
Execute one instruction out of
sequence .
The particular successor command specified then pro-
vides the controls needed in the selection (MPCR/ AMPCR ) and
incrementing logic to generate the next MpM address. Except
for the EXEC command the MPCR is loaded with the MPM ad-
dress .
For a more thorough description and discussion of
these five modules, reference 10 provides an outstanding
a5
diagrammatic breakdown of the Interpreter's internal
hardware configuration and operation. Reference 7 discusses
the interface of various Interpreter/ peripherals and memory
configurations that have been tested by the Advance
Development Organization of Burrough's Defense Space and
Special Systems Group.
In general* there are three data processing func-
tions to which the Interpreter may be applied: emulation of
existing or hypothetical machines; direct execution of high
level languages? ana problem solution through microprogram
"tuning" of the machine to the problem. The initial goal
for the installation at the Naval Pos t araduat e School is
emulation of existing machines such as the AN/UYK-7, with
further expansion and development as a teaching tool in the
areas of operating systems/ file management/ compiler writ-
ing/ and emulation of hypothetical systems.
46
B. NAVAL POSTGRADUATE SCHOOL CONFIGURATION
1 . Desc r i pt i on
The system presently installed at the Naval Postgra-
duate School consists of three Interpreters* one 64K memory
module? a card reader* line printer and dual cartridge disk.
Only one of the three Interpreters is allowed to communicate
directly with any Deripheral and is discussed below under
I/O Interface. Figure IV-2 represents the present confi-
guration; however* future expansion calls for the addition
of a supervisor's console and a cross-connection with the
school's PDP-11/45. This will enhance the attached peri-
pherals by three tape drives and greatly increase the amount
of on-line storage to the point where implementation of a
CMS-2 Compiler may be feasible.
When the system is energized and initialized daily*
its basic mi c rost rue t ure is that of two B-6700 LIFO ALGOL
Stack Machines - each with 32K of memory - attached to a
single Inout/OutDut Processor. The system is caDable of
pseudo-multiprocessing in this configuration. ALGOL pro-
grams submitted through the card reader are executed in a
batch mode with the two processors competing to fetch the
next job. All utiltiy programs* the operating system and
the file manager are executed with the machine in this con-
figuration. In order to change the machine's configuration*
the user must alter the microcode in order to execute the
desired machine such as* the AN/UYK-7.
47
L
Loader
Loader
Loader
Mi c ro/Nano
Memory
Di spl ay
Card
Mi c ro/Nano
Memory
Display
Card
Interpreter
C 1 ock
Cont rol
Processor
Loc k i ng
M i c ro/Nano
Memory
Display
Card
Interpreter
Oi sk
OOP
Swi tch
Interlock
Di sk
System
Memo r y
System
Memory
Interpreter
I
Port Select
Uni t
J^t
Printer
DDP
Card Rdr
DDP
L i ne
Printer
Card
Reader
NAVAL POSTGRADUATE SCHOOL THREE INTERPRETER SYSTEM
FIGURE IV-2
48
2. I/O Interface
Since only one Interpreter (IOP) is allowed to ex-
change data directly with the peripherals/ it is necessary
for the remaining two processors to communicate their I/O
requests to the IOP. This is done by the Interpreter plac-
ing a message in address 64K otherwise known as the "Mail-
box", and then issuing an interrupt (INT) to the IOP. The
IOP periodically tests for INT and when sensed, reads the
Mailbox, decodes the message, and performs the predefined
function. After completing its task, the IOP places a mes-
sage in the Mailbox informing the requesting Interpreter
whether or not the I/O was performed successfully. The IOP
then issues an INT to the Interpreter which sent the re-
guest. When the reguesting Interpreter receives the INT, it
reads the Mailbox to determine whether its reouest was per-
formed and continues accordingly. This method allows the
two Interpreters to act completely independently, each re-
ferencing only its assigned segment of memory and the IOP
performing all I/O asynchronously upon reauest.
3. Memory Interface
The memory module consists of a single ported, 6 4 K ,
32-bit word, core memory, which is the equivalent of 256K of
on-line, «-bit character storage. Access to this single
memory is through a Switch Interlock Unit (SwI) which makes
memory appear to be multiported to the user. The SWI acts
on a priority basis with that Interpreter having the lowest
a9
number (the IOP) given the highest priority. Once an Inter-
preter issues a memory read/write reference/ it may continue
execution and need not wait on a memory completion signal.
However/ the memory address register (MAR) on a Read/Write*
and the Memory Information Register (MIR) on a write/ should
not be changed until a completion signal is received. Thus
a mi c roprogramme r who anticipates his memory accesses and
intersperses these instructions among the other code/ should
never have a delay caused by memory referencing.
C. INSTRUCTION TIMING
The Interpreter uses a one megahertz clock and initiates
a new microinstruction every microsecond. The Interpreter
enhanced with Emitter Coupled Logic (ECL) and a higher speed
memory can operate off an 8 Megahertz clock. A correspond-
ing 8-fold improvement in execution times can be expected.
There are two basic instruction types in the Inter-
preter. Type I uses two phases (I and III) for execution;
although/ its phase III may be held in abeyance until com-
pletion of a subseauent Type 11/ which always uses only
phase I to complete. Phase I of the following Type I in-
struction always overlaps Phase III of the previous Type I.
Type I instructions involve condition testing/ external
functions and Adder/Logic operations. Type II instructions
involve literal assignments to one of three registers (LIT,
SAR and AMPCR). Appendix 0 of reference 9 contains an ex-
cellent discussion of instruction timing.
50
D. LANGUAGES
The D-Machine has two resident programming languages:
the language of the operating system, ALGOL; and the mi-
croprogram assembly language* TRANSLANG.
1. ALGOL
The resident programming language of the Burrough's
D-Machine is the ALGOL 60 Language enhanced with additional
language constructs which oermit manipulation of data in the
form of character strings. ALGOL employs a vocabulary of
reserved words and symbols. The structure of the language,
syntax, reserved words and symbols, and additional features
of the ALGOL implemented on the D-Machine are discussed in
reference 10. The accepted character set for ALGOL varies
depending on the machine used and the character set or sets
available on the machine. The Naval Postgraduate School
configuration reguires that all characters be converted from
EBCDIC into the 6-bit Burrough's Common Language (BCD for-
mat for recognition by ALGOL. This conversion is performed
by the I0P when it is used for interfacing communications
from external devices to the other Interpreters. When
information is directed to an external device the IOP
performs a reverse conversion, from BCL to ASCII. Thus all
inputs to the emulator from oeripherals are 8-bit characters
containing a 6-bit BCL code. The Interpreter's file
management routines, operating system and utilities are
written in ALGOL, for execution on the ALGOL Stack Machine
51
configuration. ALGOL source modules mav be inputted to the
ALGOL Compiler from disk or caras. Object modules are
placed in user libraries on disk for future execution by the
stack machine. The operating system (MCP) will load specif-
ic object modules for execution when it recognizes a H?RUN
filename" control card * where filename is assumed to be a
precompiled ALGOL program.
2. TRANSLANG
The mi c roprogramme r is aided in producing micropro-
grams by a Mi c rot ransl at or/Assemb 1 er that translates symbol-
ic instructions written in TRANSLANG into microinstructions.
Reference 9 describes the structure of TRANSLANG by defining
its syntax and semantics* and presenting a series of exam-
ples. The reference also includes descriptions of register
state changes resulting from executing microinstructions.
Interoreter controls and timing are explained. Coding tech-
nigues and conventions are discussed via sample programs.
The reference analyzes external operations with main memory
and perioheral devices* and the coordination and control of
multiple Interpreters via the Switch Interlock and global
condi t i on bits.
The Mi c rot rans 1 at or is written in ALGOL for the 0-
Machine. It is written modularly with each function setup
as a procedure call. The language* TRANSLANG* used ALGOL as
a model* however* almost the entire language is composed of
reserved words. Reserved words have very specific meaning
52
to the translator and cause specific nano instructions to be
develooed. TRANSLANG is free form and each instruction may
be written in almost any order? however/ multiple instruc-
tions appearing on the same line or card must be separated
by a period. Each TRANSLANG instruction corresponds to one
microinstruction; which is the set of Interpreter functions
performed in parallel at each machine clock. The constructs
provided include iterative mechanisms* I/Of Boolean, logical
and computational operations/ control transfers/ and assign-
ment functions. In order to provide control points for
transfer operations/ each instruction may be labeled with a
symbolic M-Address. The output module of the M i c ro t rans 1 a-
tor is placed on aisk and when loaded into micromemory/
alters the basic machine configuration. Reference 9 is used
as the m i c roprogramme r ' s programming manual/ although/
there have been several enhancements to the machine and
language which are not included in the manual. These modif-
ications are discussed in Apoendix A of this thesis.
53
V. PROJECT DESCRIPTION
The AN/UYK-7 achieves its speed and versatility par-
tially through concurrent field utilization and partially
through the provision of special and general purpose regis-
ters. Its emulation is complicated by the various modes of
instruction operation (repeat* indirection/ indexing) and in
particular by the use of ad hoc addressing techniques. The
fact that the AN/UYK-7 performs many of its operations in
parallel makes it difficult for an emulation which is imi-
tating one facility at a time to run in AN/UYK-7 real-time.
For the remainder of this discussion the acronyms A(a)/ B(b)
and S(s) refer to the Accumulator, Inaex and Base registers*
respectively. The subscripts (a* b* and s) correspond to
the register specif i e o in the cognizant field of the in-
struction* and may assume values of 0 to 7. CaDitol "Y"
refers to the effective 18-bit* operand address; small " y "
refers to the 13-bit* y-field of the instruction. The com-
bination sy-field is formed by concatenation of the 3-bit*
s-field and 13-bit* y-field of the instruction and forms an
alternate operand address.
During the initial analysis of the Emulation it was de-
cided to separate the project into the following phases:
First* the machine would be designed to accommodate a
full emulation includinq multiprogramming and all IOC
5a
functions. This required that all registers and condition
bits of the actual AN/UYK-7 hardware be mapped into the
model* even if they would not be used during this partial
Emu 1 at i on •
Second/ it was decided to divide the Instruction Reper-
toire into the followinq groups:
a. Those instructions that could be emulated im-
mediately ana tested completely; such as/ all
Format I's and II's except Multiply* Divide*
Square Root and Double Register Operations.
b. Those instructions that could be done prior to
completion but for which there might be insuf-
ficient time for complete testing; such as* all
Format Ill's* Shifts* Multiply* Divide* and
Double Register Operations.
c. Those special instructions and functional modes
that would be incorporated if at all possible;
such as* indirection and repeat.
d. Those features for which there would definitely
be insufficient time for incorporation; such
as* Interrupts* IOC Instructions* and Floating
Point Ooerat ions.
Third* a "Loader" program which could reaa AN/UYK — 7
instructions from cards* decode them and place the results
into memory for execution by the Emulator was mandatory.
Fourth, some facility for monitoring and debugging
each instruction as it is executed by the Emulator would be
requ i red .
55
Fifth/ some facility to output the results of each
AN/UYK-7 program and to input test data was needed.
To accomplish these five tasks* two basic programs
called the "Loader" and the "Emulator" were written. Each
of these programs occupied its own Interpreter whenever the
system was reconfigured as an AN/UYK-7.
A. LOADER
The Loader was written in TRANSLANG and fulfilled the
third/ fourth and fifth reau i rement s / that is» it served as
a combination loaoer, deougger and IOC monitor. Its use is
described in Appendix A, the User's Manual section of this
thesis. In general/ the loader portion of the program acts
like a pseudo-assembler. It has macros for defining a con-
stant or character string/ for saving space/ for initializ-
ing registers and switches/ and for inputting instructions.
The loader will accept one instruction per card and deter-
mine whether it is a Format (1/ 11/ III/ I V - A / or IV-B) in-
struction. Based on this determination/ the Loader will
decode the specified fields from the card and generate a
binary instruction which is placed in the next sequential
location in the user's memory. Upon detecting an "N" card/
the loader portion of the program signals the Emulator
which is resident in the alternate Interpreter - that
instructions are available for execution.
56
At this point the loader function ceases ana the program
can be called upon by the Emulator to act as a debugqer or
as an IOC. As a debugger, the Loader can be used to gen-
erate a number of error messages to the operator* or to pro-
vide an actual dump of control memory registers 000 to 035,
which includes all Task Registers, the PAR and the Active
Status Bits. As an IOC, the Loader can be called upon to
read a card, print a buffer, or read the disk.
It should be emphasized that the Loader was written
strictly as a tool to assist in the development and testing
of the Emulator. Presumably, once a full emulation is writ-
ten and tested, the IOC functions will be incoroorated into
the Emulator, while the loader and debugger functions will
be either written in ANl/UYK-7 Machine Language, or absorbed
by the Emulator. When this is done, the Interpreter previ-
ously utilized by the Loader will be free for loadina as a
second AN/UYK-7, and a true multiprocessing environment
could be created. A cooy of the Loader is Drovided in Ap-
pendi x C .
B. EMULATION PROGRAM
The Emulator was written in TRAM SLANG microcode, and is
loaded directly into the Interpreter's micromemory from
disk. A cooy of the Emulator is provided in Appendix B.
Overall program flow for the Emulator is presented in Figure
V-l .
57
A
iCl
no
yes
Fetch Next
Instruction
Isolate Opcode
no
yes
Isolate "B"
Index Field
Branc h to
Oocode Subroutine
-f
rs
Print "ILLEGAL
Inst rue t i on
Isolate Lower
Ha 1 f word
OVERALL PROGRAM FLOW
FIGURE V-l
58
Besides the necessary Control Memory Registe'r mappings,
it was necessary to minimize memory references by maintain-
ing certain frequently used information in the D-Machine's
internal registers. For this reason, the PAR is maintained
in the lower 20 bits of the D-Machine's A2 register. The
upper 12 bits of fl2 are used to maintain some of the most
frequently referenced bits of the AN/UYK-7's Active Status
Register as listed in Table V-l.
ASR Bit
A2 6i t
Func t i on
2
1
0
3
8
9
10
1 1
N/A
N/A
15
N/A
31
30
29
28
27
26
25
2a
22-23
21
20
0-19
Equa 1 /Unequa 1
Greater Than/Equal
Limits
Fixed PT Overflow
Task use of 05-a
Remove Interrupt Lockouts
Int/Task Accumulators
Int/Task Base Regs.
0 1 = I nd i rec t i on
10 = Optional Indirection
11 = Character Addressing
Repeat Mode
Halfword Indicator
PAR
ACTIVE STATUS REGISTER
TABLE V-l
The remaining bits in the ASR are not used in this Emu-
lation, but if needed could be mapped into any unused loca-
tion in memory below address 102a.
The D-Machine's Al reqister is used to maintain a copy
of the instruction currently being executed. All other re-
gisters are free for computational use. The D-Machine's
59
General Condition Bit One (GC1) is reserved for communicat-
ing with the Loader. General Condition Bit Two (GC<?) is
used to indicate that an AN/UYK-7 instruction is being exe-
cuted under a special condition; such as, repeat mode or in-
di rect i on .
The Emulator consists of an Opcode/Sub-oocode Directory/
an instruction fetch routine (IFETCH), global subroutines
and opcode execution subroutines. When the Emulator re-
ceives a signal from the Loader (GC1) to commence excut ion>
it immediately passes control to IFETCH, which reads the PAR
and places the first instruction in Al. The opcode portion
of the instruction is isolated and used as a pointer into
the Opcode Directory. Control is then passed to the opcode
execution subroutine designed to handle that particular in-
struction. The opcode subroutines may stand alone and per-
form their functions independently? or they may call several
global subroutines used to consolidate code for multiple op-
codes. Upon completion of its execution* the opcode
subroutine oasss control back to IFETCH which then fetches
the next instruction.
In the case of halfword instructions* control is passed
to HALFFETCH which serves the same purpose as IFETCH, except
for 16 bit instructions. Every attempt is made within the
opcode subroutines to do in-line coding versus subroutine
calls. This decreases execution time considerably;
although, it greatly increases program size. During the in-
itial orogrammina phase the Interpreters were limited to a
60
4 K micromemory due to the dynamic overlay routine (SMX) be-
ing positioned at 4k. As a result* excessive subroutine
calls were necessary in order to keen the program size below
4K. This software deficiency has since been corrected by
Burrough's and a full 8K micromemory is now available.
These subroutine calls could now be removed and the
subroutines moved back in-line.
Emulation of Central Processor instructions in the
AN/UYK-7 repertoire was fairly straightforward. Most in-
structions were implemented with an average of 15 microin-
structions. This generally included: isolating the various
fields/ forming the effective operand (Y) address* fetching
the operands from main memory/ performing the instruction
function^ and writ ino the result back to main memory/ com-
monly referred to as S-Memory. Because of the parallelism
of the D-Machine's nano i nst rue t i ons several of these func-
tions were performed simultaneously. M a n y AN/UYK-7 instruc-
tions have sub-opcodes/ each of which perform a different
operation on the same operands. In such cases/ the opcode
subroutine centralized code by performing the field isola-
tion and operand fetch functions prior to calling the sub-
opcode subroutine. Either the ooerand itself or its address
was passed in a register to the subroutine/ which then per-
formed its function and wrote the results back to S-Memory.
The difficulties arose in the AN/UYK-7 Emulation when
the repeat and indirection modes of operation were imple-
mented. The Repeat Instruction reguired that the next
61
sequential instruction be executed the number of times con-
tained in the Index Register 6(7), or until specified alter-
nate conditions were met. This required that flags be set
indicating that the repeat mode had been initiated and that
special termination conditions were to be tested. Condition
testing took place after each execution of the repeated in-
struction and prior to return to IFETCh for the next in-
struction. If the conditions were not satisfied IFETCH was
bypassed and the same instruction was reexecuted after first
decrementing B(7), and then indexing the ooerand address by
the displacement value contained in the repeat instruction.
If the conditions were met the normal IFETCh mode was exe-
cuted and the repeat mode was terminated. Most instructions
requirea checking the condition of a specified accumulator
register to signal completion of the repeat mode; however,
compare instructions used the results of their comparison to
signal completion. Repeated replace instructions used a
different Y-ooerand calculation for their store phase then
for their fetch phase. Instructions that were not designat-
ed as being repeatable were executed once and the repeat
mode was terminated. A copy of the Reoeat Instruction was
saved in S-Memory at address 0030; a copy of the instruction
beina repeated was saved at address 0031; and the Y-operand
address used for storing during a repeated replace instruc-
tion was saved at 0033. These addresses are given in octal
and are normally unused in the AN/UYK-7.
62
The indirect modes of operation possible in the AN/UYK-7
were extremely difficult to emulate. There are four modes
of inairection possible: Normal Indirection, Character Ad-
dressing, Sequential Character Addressing, and Optional In-
direction. Not all instructions are indirectable and some
instructions are indirectable but not character addressable.
To make this determination a table was created in the Emula-
tor which would return a value based on the instruction op-
code. This value indicates whether an instruction is re-
peatable* indirectable, or character addressable. All mooes
of indirection are initially signalled by the i-field of the
instruction being a one. This indicates that the Y-operand
points to an Indirect Control Word (ICW). The ICW, which is
presented in Figure III-l, is then fetched and its bits 30-
31 are examined to determine the indirection mode. In all
cases, if the i-field of the I C w is set, the Y-operand again
points to a new ICw. The Y-operand is calculated in accor-
dance with the indirect mode. Operand fetching will contin-
ue in this manner, cascading through memory, until an ICW is
found without its i-field set. At this point the lower 2 0
bits of the ICrt replaces the lower 20 bits of the original
i nst rue t i on .
Normal indirection is indicated by a binary 10 in bits
31-30 of the ICW. Y-ooerand address calculation is per-
formed as Y=y+B (b) +S ( s ) . Once the final ICw is determined
then normal execution of the instruction resumes.
63
Single Character Addressing is indicated by a binary 01
in bits 31-30 of the I C W . Y-ooerand address calculation is
performed as Y=y+6 (b) +S ( s ) ; however* in this mode two addi-
tional fields (P/rt) of the I C W are meaningful. The P-field
indicates the least significant bit position of the charac-
ter to be fetched from the operand and the W-field indicates
the number of bits in the character. When the character is
fetched - it is right justified; operated on in accordance
with the instruction; and then (deoendinq on the instruc-
tion) ORed back into its original position in the Y-operand.
Seguential Character Addressing indicated by a binary 11
in bits 31-30 of the I C W , operates in exactly the same
manner as Single Character Addressing except in the case
where the store cycle is reguired. Before ORing the result-
ing character back into the Y-operana the P and w-fields are
compared. If P minus W is positive then the difference re-
places P and the character is stored accordingly. If the
difference is negative then 32 minus IN replaces P and the
"svH field of the I C .^ is incremented by 1 and replaced in
memory for the next execution.
Optional Indirection is indicated by a binary 00 in bits
31-30 of the ICW. In this mode bit 29 of the ICW is also
significant and modifies the Y-ooerand address calculation.
If bit 29 is 0 then Y=sy+S(b). If bit 29 is 1 then
Y=sy*B(b)+(S) , where S is designated by bits 17-19 of B(b).
Once the first operand is fetched then normal instruction
execution occurs.
6a
A large portion of the Emulation code was devoted to
handling the four modes of indirection and its ad hoc ad-
dress calculations. General Condition Bit 2 (GC2) was used
to flag the indirect and repeat modes of operation. Address
0 0 32, octal f in S-Memory was reserved for saving the current
ICw being used during Character Addressing; address 0033,
octal, was reserved for the Y-operand address in the case of
optional indirection; address 0034, octal, was reserved for
the address of the current ICW which could be updated during
seguential character addressing. These addresses are part
of the Control Memory Registers and are not normally used in
the AN/UYK-7.
Although the IOC has not been emulated, Input/Output
functions were implemented which make the systems' peri-
pherals accessible to the user. The AN/UYK-7 Initiate I/O
instruction was implemented in the Emulator with the excep-
tion that the a-field, which is normally used as a channel
designator, actually Designates the desired peripheral.
Based on the contents of the a-field, a function code is
formulated and passed to the IOC portion of the Loader. The
Emulator then enters a neutral state awaiting an Interrupt
from the Loader that the I/O has been performed. The Y-
operand address of the I/O instruction fetched by the Emula-
tor points to the address of the buffer, rather than to a
Duffer control word as in the AN/UYK-7. It was felt that
65
implementation of I/O in this manner would remain virtually
transparent to the user, and would facilitate full emulation
of IOC functions at a later date.
Of the 132 instructions in the AN/UYK-7 Repertoire* 111
have been fully implemented and tested. One instruction
(Return Jump) has been implemented but not tested. Twenty
instructions remain to be both written and tested. All
unwritten instructions were assigned space in the Opcode
Directory and» if used by the programmer, will cause an er-
ror message to be printed to the effect that the instruction
has not been yet implemented. The implementation of these
instructions involves developing the required microcode and
inserting it into the soace already allocated in the Opcode
Subroutine Library. The un i mpl ement ed instructions include
all Floating Point Operators, Scale Factor, and Interrupt
Hanoi ers .
The Repeat Instruction and its associated mode of opera-
tion have been imolemented and tested with the exception of
the repeat replace instructions, which have been written but
not yet tested. Indirect addressing has been fully imple-
mented but has not been tested. Input/Output functions of
the IOC have been implemented and tested allowing the user
to read a card, print a buffer, or read a disk sector. The
disk write function has been designed into the Emulator but
not imolemented for fear of destroying resident disk materi-
al during execution. This function should not be fully em-
ployed until either a monitor svstem is developed which
66
would DPeclude write access to assigned disk sectors* or the
assumption is made that the entire disk is available to the
user as a scratch pad.
C. REGISJER MAPPING
Because the D-Machine has few registers available to the
user* the authors chose to mao all of the AN/UYK-7 registers
into main memory. In addition* it was necessary to create
several special locations to hold temporary results or con-
ditions. In order to facilitate this mapping, all memory
locations below 1024 decimal are reserved? thus* all user
instructions and memory references were offset by this
amount by the Loader. Since this Emulation will be in a
monoprogramming environment* all Base Registers were ini-
tialized in increments of 8K with the first Base Register
set to \0dU. This allowed user access to approximately 63K
of main memory* with each Base Register referencing an 8K
page of memory. The Control Memory Register (C^R) alloca-
tions and additional temporary mappings (indicated by an *)»
are presented as part of Figure V-2. The registers marked
"*M are not used in the AN/UYK-7* and were thus assigned
special purposes in the Emulator. Additional unused regis-
ter areas are available and labelled "unused" in Figure V-2.
These register areas could be employed for the same purposes
if needed in the course of expansion to a full emulation.
67
OCTAL
ADDRESS
DECIMAL
ADDRESS
DESCRIPTION
0-7
10
11-17
20-27
*30
*31
*32
*33
*34
*35
36-57
60-67
70-77
100-107
1 10
111-117
120-127
* 1 30
131-137
iaO-157
160-167
170-177
*200
*201
*202-2U6
*247-323
*324-357
360-365
*366-426
427-437
*aao-i777
2000-77775
*77775-77776
0-7
8
9-15
16-23
2a
25
26
27
28
29
30-47
48-55
56-63
64-71
72
73-79
80-87
88
89-95
96-103
104-1 1 1
112-1 19
120
121
122-166
167-21 1
212-231
232-237
238-270
271-279
280-1023
1024-65533
65534-65535
Task
Unus
Task
Task
Repe
Cur r
Cur r
Y-op
ICW
Prop
Unus
Inte
Act i
Int .
CP M
Int .
Int .
Swi t
Unus
Des i
Stor
Segm
Loca
Real
Di sk
Di sk
Card
Unus
Prin
Unus
Erro
User
Mai 1
A-Reg.
ed
Index
Base S
at Inst
ent Ins
be i ng R
ent Ind
Cont rol
e rand f
Address
ram Add
ed
rrupt B
Regi ste
ve Stat
A-Reg
o n i tor
Index
Base
ch Valu
ed
gnat or
age Pro
Regi ste
ent Ide
Regi ste
t i on Co
Time C
Input
Output
Input
ed
ter I/O
ed
r' Rout i
Progra
box
(0-7)
B-Reg. (1-7)
-Reg. (0-7)
rue t i on Temp •
t rue t i on
epeat ed
i rec t
Word (ICW)
or Indi rec t i on
i n Memo ry
ress Regi st er
reakpo i n t
rs (0-7)
us Words (0-7)
i sters (0-7)
Clock
B-Reg. (1-7)
S-Registers (0-7)
es Temporary
Storage Words (DSW)
tection
rs (SPR)
nt i f i cat i on
rs (SIR)
unt er
1 ock
Buffer
8uf f er
Buffer
Buffer
nes
m Area
♦•Temporary Location Established By Programmers Convention
REGISTER - MEMORY MAPPING
Figure V - 2
68
D. TIMING
Although no formal timing survey was conducted* an
analysis of the Emulation itself provided an indicator which
was used in developing a comparison to real-time. For this
analysis it was assumed that each instruction was executed
using direct addressing and not in repeat mode. The IFETCH
routine used 16 microseconds which was an automatic overhead
acguired by all instructions. The operand fetch and store
routines (YFETCH, YSTORE and Y2FETCH) added an additional
33* 30* or 14 microseconds* respectively. Thus any in-
struction which referenced a Y-oDerand incurred an addition-
al overhead of 14 microseconds at a minimum. Adding to this
overhead* the execution time of the basic oocode itself
yielded the time estimated for typical instructions given in
Table V-2.
INSTRUCT ION
TIME
OPERANDS
EMULATION
TIME
AN/UYK-7
TIME
Load
Add
Add
Di v i de
Reai st er * Y
Regi st er * Y
Regi st er
Regi st er * Y
60
63
36
600
1.5
1.5
1.0
15
TIME ESTIMATES
TABLE V-2
b9
Using these figures it was estimated that this Emulation
ran on the order of 40 times real-time. Two steps could be
taken that would considerably improve this time. First*
move all out -of - 1 i ne subroutine calls in-line in the opcode
subroutines. Second* enhance the Interpreter as discussed
under Instruction Timing in Chapter III. It has been es-
timated that this same Emulation could run at approximately
5 times real-time on an enhanced D-Machine. This time com-
pares favorably with a Simulation of the AN/UYK-7 written in
PL-560 for the IBM 360, which runs on the order of 1000
times real-time. As discussed in Chaoter II, it would be
difficult to approach real-time in emulating the AN/UYK-7
because of the parallelism of its fetch and field isolation
operations. The addition of a Field Select Unit (FSU) and
additional internal temporary registers would be reguired
before a real-time emulation could be realized.
70
VI. SUMMARY
The authors' conclusions and recoir^endations resulting
from any research project are a fundamental part of the for-
mal presentation and are therefore included in this thesis.
In addition/ the authors felt that the reader? who might be
contemplating an emulation project* would be interested in
the problem areas encountered during the pursuit of this
thesis. Accordingly this chapter is divided into two sec-
tions - Problems and Conclusions.
A. PROBLEMS
During the course of this emulation numerous software
and hardware problems were encountered * h i c h had a consider-
able effect on progress and the amount accomplished in the
allocated time. Software problems stemmed principally from
poor documentation of the D-Machine, the AN/UYK-7, their as-
sociated languages and internal configuration. The software
problems with the D-Machine were generally resolved through
experimentation on the machine or through phone calls to
Burrough's Advanced Development Organization (ADO). The
lack of thorough AN/UYK-7 documentation proved to be a more
severe handicap since no test base for experimentation was
accessible at the Naval Postgraduate School. Such a medium
is absolutely mandatory when working in the emulation
71
environment. The programmer must be able to determine the
machine reaction to unorthodox instruction configurations.
Some degree of assistance was proviaed by the Fleet Combat
Director Systems Support Activity (FCDSSA), San Diego; how-
ever/ in some cases the result was a "best guess" as to what
the AN/UYK-7 response would be.
Hardware Droblems are to be expected during the course
of any major project and particularly when a new machine is
involved. This Emulation was the first Droject to be under-
taken on the Naval Postgraduate School's D-Machine since the
machine was installed. The estimated mean-t i me-bet ween-
failures (MTBF) experienced by the authors was less than
five hours. Problems ranged from loose circuit boards ana
dirty contacts/ to aisk read/write heaa misalignment. Un-
fortunately/ the time to reoair was agcravated by the fact
that the school has no technicians trained on the D-Machine/
and the authors were i nexoer i enced in its maintenance and
operating procedures. without the assistance provided by
Burrough's ADO the project could not have been seen through
to fruition. The ADO Drovided the school with engineering
assistance on three separate occasions/ the last of which
uncovered a major design problem. The machine has since
been modified and the system is presently very reliable.
72
In addition to these two major pro clem areas progress
was inhibited by the following:
1. Lack of Software Utilities - Since the D-
Machine was a new installation the school
has not had the opportunity to generate the
numerous desirable software utilties. In an
effort to eliminate the inherent slowness of
a "Card Only" system, the authors have un-
dertaken the implementation of the
supervisor's console as an adjoint to this
thesis. The authors are also implementing a
Text Editor which will allow for on-line
program modification, and will replace the
present card input Line Editor.
2. M i c roorogramm i ng is not a new conceDt at the
Naval Postgraduate School; however, actual
experience was lackino. The Computer Sci-
ence Department has played a Tiajcr role in
implementation of the D-Machine and the re-
guired expertise is rapidly oeing developed.
3. The learning curve for undertaking an emula-
tion is tremendous. The target machine, the
host machine, their respective programming
languages and internal configurations must
be learned and understood in minute detail.
4. The target machine for this Fmulation, the
AN/UYK-7, is an extremely soohisticated and
difficult to understand comcuter. The cen-
tral processor instruction set is fairly
straightforward and easy to implement; how-
ever, the numerous and differing modes of
operation severely complicated the Emula-
tion.
B. CONCLUSIONS
The authors feel that they have successfully achieved
their goal of demonstrating the feasibility of emulating the
AN/UYK-7 on the Burrough's D-Machine. The design oresented
in this thesis is a workable design as evidenced by execu-
tion of AN/UYK-7 programs successfully and by execution in
73
less than 4 0 times the actual execution time of the A N / U Y K -
7. Better than 90% of the AN/UYK-7 Instruction Repertoire
has been implemented and tested* thus providing a sound
foundation for a full emulation. The design allows for ex-
pansion to a full emulation which wouH include the IOC in-
struction repertoire and Floating Point without major modif-
ication. Further* the authors have concluded that by modif-
ication of the design to place out-of-line subroutine calls
in-line and enhancement of the D-Machine* the Emulation
would execute within 5 times the actual speed of the
AN/UYK-7.
During the course of this oroject the authors had an op-
portunity to visit the Naval Surface Weapons Center (NSWC)*-
D a h 1 g r e n * Virginia. Emulation in aeneral was discussed with
the programming staff* who had just completed emulation of
the Trident Computer on the Nanodata Q 'v - 1 * and who were con-
temolating emulating the AN/UYK-7 on the QM-2. Based on
these discussions* the experience gainec in the course of
this thesis* and presupposing the oresent level of knowledge
of the authors? it is estimated that a complete emulation of
the AN/UYK-7* its IOC and all Interrupt functions would re-
guire an additional 2 man years of procramming effort. This
estimate includes a reasonably sophisticated degree of test-
ing* and assumes full accessibility of the D-Machine and an
AN/UYK-7 test base.
7a
VII. RECOMMENDATIONS
The authors feel that this thesis has provided them
with a learning experience previously unparalleled in either
of their lives* since it has entailed detailed ana indepen-
dent learning of emulation, microprogramming (TRANSLANG),
the Burrough's D-Machine and the AN/UYK-7. In addition, the
authors became part time technicians in an effort to keep
the D-Machine running. It is felt that the same educational
horizons await any student considering a similar project;
however, in an effort to k e e d others from having to "rein-
vent the wheel", the authors have included much of what was
learned about these subjects in this thesis. Hopefully, by
building on these experiences, others will be able to begin
at a much higher level and consequent ly accomplish more.
The following recommendations are submitted for considera-
tion bv anyone inclined to undertake a fhesis involving emu-
lation.
1. Do no try to emulate a machine that uses
hardware interrupts on an Interpreter that
does not have interrupts.
2. Pick a taraet machine that is well defined
and documented. Computers are designed to
perform a soecific set of functions? the
results of unorthodox use are not always
known, but must be considered by the emula-
tor. The availaoility of a target machine
for testing to determine such results is
mandat ory .
75
3. Ensure that the host Interoreter is well
documented and has a reasonable set of sys-
tem utilities? such as> an editor, de-
bugger, simulator, file manager, operatinq
system and compiler.
4. Ensure the host Interpreter will receive
hardware support if problems arise.
5. Ensure publications are available covering
utilites, hardware, languages and
target/host machine capabilities and opera-
tion.
6. Be preoared to work independently and have
your questions answered through your own
experi ment at i on .
In addition to these recommedat i ons , the authors would
like to propose several thesis topics applicable to the D-
Mach i ne .
1. Several projects could be undertaken
direct follow on to this thesis:
as
An Ooeratina System, File Manager,
and Assembler could be written in
AN/UYK-7 machine language utilizing
the existing Emulator.
The present Emulation could be
enhanced to include Floating Point
and any un i mp 1 emen t ed instructions,
including incorporation of the IOC
functions and allowing for synchro-
nous I /0 .
A timing survey could be conducted
comparing the existing Emulation with
AN/UYK-7 benchmarks.
2. . Several thesis projects are possible which
entail enhancing the capabilities of the
existing O-Machine Installation. These in-
clude writing the interface to tne PDP-
11/45, ana a resident Text Editor.
76
The stand alone environment of the D- Machine lends it-
self to experimentation with the design of operating systems
and file managers.
In summary* the authors would like to state that they
found the D-Machine an outstanding learning device in spite
of its many hardware problems. The authors found the abili-
ty to emulate existina computers exciting, and found the
realization that they could build a working model of any
computer they could desian, exhilarating.
77
APPENDIX A. USER'S MANUAL
A. D-MACHINE
When the D-Machine was installed at the Naval Postgra-
duate School* it was not accoitioan i ed by any form of documen-
tation for its operation* preventive maintenance* diagnos-
tics or utility programs. For the most part this informa-
tion has been derived through exoerimentation and freauent
calls to Burrough's ADO. Some of the more pertinent infor-
mation is included in this User's Manual to enable the user
to load and run a proaram such as the AN/UYK-7 Emulation.
Unless specified otherwise all addresses given in this dis-
cussion are in hexadecimal.
1. System Initializing
The machine is secured every night ana must there-
fore* be reinitialized when powered uo each morning.
a. Ensure circuit breakers 2* 7 and 10 are on.
b. Push the "ON" button on the disc and all
three Interpreters.
c. With desired discs in the drives* push the
two "RUN" buttons on the disk unit.
d. Turn on the card reader and printer.
e. Place the IOP in normal vice single step
mode via the switch inside the cabinet on
the right.
78
f. Push the "LOAD" button on the IOP; then
push "CLEAR".
g. Place the cards marked IOP-Loader into the
card reader. Cards should be read and the
IOP should stoD at an MPAD of OOFA. If
not t repeat steps e through a.
h. Push the "LOAD" button on IOP to return the
IOP to norma 1 .
i . Perform steos e to h for each of the other
two Interpreters using the cards marked
STK-loader. They should halt at a MPAD of
004A.
k. Push "CLEAR" on each Intreoreter. They
should bootstrap themselves through the IOP
and halt at either 0542 or 051A. (An In-
terpreter must be at 0542 to run a program
and only one Interpreter can be at 0542 at
a time.) Clear the IOP to force an Inter-
preter to switch from 051A to 0542.
The D-Machine now thinks it is a Burrough's B6700
single-stack machine. Any utility can be run using the
proper control cards as documented in the computer lab. The
more common utilities are Sunrise (updates the day* date and
time? should be run first thing every morning), Dir-List
(prints out the directory; system or user), Compile (com-
piles ALGOL programs) and TRANSLANG (assembles micropro-
grams). By use of the orooer control cards, the user can
also obtain a source listing of his program as it is being
compiled or assembled. Actually the default is a printout
every time and the user must insert a " $ - 1 i s t clist" control
card to eliminate the listing.
79
To make the computer act as some machine other than
the B6700, use the control card "7SMLQAD filename". The "?"
must be in column one and the rest of the card is free-
format. This loads the microprogram "filename" (which must
be an assembled T R A N SLANG program) into micro-memory over-
laying the stack machine and then transfers control to that
program starting at address 0000. Thus to load the AN/UYK-
7, execute "?SML0AD UYK7-L0ADER" on one Interpreter and
"7SML0A0 ANUYK7-EMULAT0R" on the other. Refer to the ao-
propriate sections of this chapter for further instructions
on the execution of these programs.
2. Diagnostics
The orograms used for diagnoscing hardware problems
are written in TRANSLANG and maintained as object modules on
cards. The approDriate orogram is loaded in the same
fashion as the bootstrap loader and terminates at a signifi-
cant address. When "cleared"* it should aaain terminate at
an address which indicates success or failure. The operator
must determine which from the program listing* as no mes-
sages are printed. There are no diagnostics written for the
disk* printer or card reader. At the present time a CRT
terminal is hooked ud to the 1 0 P * however* there is no
software supoort for it. An interface is being written into
the operating system and eventually all commands to and from
the operator will be via the CRT. The card reader and line
printer will then be strictly data I/O ports.
80
3. Debugging
While executing any T R A N SLANG program, the user can
monitor the program by use of the nixie light display panel
and the function switch assigned to each processor. The
lights indicate hex numbers. By selecting the appropriate
function the user can observe the current nano i nst rue t i on
being executed? the address of the current microinstruction
(MPAD); the memory address last written to or read from
(B^Atf); and the MIR register (MIR and EXT). The MIR func-
tion displays the lower 16 oits of the mir register while
the EXT function displays the upper 16 bits. These func-
tions are presently the only means of debuggina. For exam-
ple, if the user were unsure of the information being read
from S-memory, he could insert two additional instructions
in the code: an instruction to olace the data into the MIR
register and a "WAIT" instruction. The CPU halts at the
"WAIT" instruction and the user can then examine the infor-
mation in MIR to ascertain its validity. The user may
check the MPAD to determine if the address read was actually
the address intended. To continue the program the user must
press the force-step button inside the side panel. If the
user wished to step through a series of instructions follow-
ing the "WAIT", he could go to single-steo, and while hold-
ing the force-step button, press the single-step button to
override the "WAIT". After passing the "WAIT", single-step
to execute one instruction at a time. In this manner the
user can debug several instructions one at a time.
81
B. AN/UYK-7
This section of the User's Manual discusses how the user
can reconfigure the D-Machine into an AN/UYK-7.
First, ensure that the disk packs which are mounted
are the AN/UYK-7 System Packs and that both in-
terpreters are loaded with an ALGOL Stack
Mach i ne .
Second, insert an "7SML0AD UYK7-L0ADER" card in the
card reader. This will cause the Loader's mi-
crocode to overlay the stack machine's micro-
code and stop at address "0000".
Third, insert an "7SML0AD UYK 7-EMULATOR" card in
the reader. This will cause the Emulator's mi-
crocode to overlay the alternate stack machine
and stop at address "00A0". The AN/UYK-7 is
now ready to accept and execute programs.
Fourth, place the AN/UYK-7 source programs in the
reader and force step the Loader and the Emula-
tor, respectively. The Loader will read one
card at a time, decode it and place the 32-bit
resulting instruction in memory for subseauent
execution by the Emulator.
The last instruction of all user programs shoula be a
"HALT", which will cause the Emulator to halt ana the Loader
to be reinitialized for the next job. Force stepping the
Emulator after the halt will cause the next job to be read
and executed. Use of this convention permits batch process-
ing of programs by the AN/UYK-7. The orogram deck organiza-
tion is discussed in the next section. Individual programs
are separated by "N" cards.
82
1 . Loader
a . Macros
This section describes how a program must be
keypunched for input to the Loader. All Macro control char-
acters and formats are listed in Figure A-l. Any character
typed in column one» which is not listed, will cause an
"Illegal Instruction" message and the card will be ignored.
It is noteworthy that all functions are optional with the
exceotion of the "N", which must terminate the program deck.
All addresses are in octal and considered absolute as far as
the user is concerned; however, they are offset by 1024 by
the Loader. Macros and instructions may be interspersed as
des i red .
83
COL. COL.
1 4-8
FUNCTION
A" Reaister 0-7
Cols. 9-19 contain tne octal value
to be inserted in the listed A-Reg
I" Register 1-7
Cols. 9-19 contain the octal value
to be inserted in the listed B-Reg.
"D" Octal Address
Cols. 9-16 contain the decimal value
to be inserted at the address listed
or in-line if the address=0000 .
"R" Octal Address
Cols. 9-19 contain the decimal number
of words to be saved at the address
listed or in-line if the address=0000 .
"W" Octal Address
Cols. 9-80 contain the character string
to be inserted at the address specified.
The string terminates before col. 80 if
a single quote (') is encountered.
"S" Switch Value
Cols. 6-8 contain an octal number
whose bit Dattern selects which of
eight AN/UYK-7 switches the user
desires set .
ML" Octal Address
Causes Base S-Registers to be set
at 8K cages starting at 1024, and
the program to be loaded at Address.
"0" Octal Address
Causes change in the program counter in
order that subseguent instructions may
be loaded at Address.
MN" Octal Address
Terminates loading of program and
initializes PAR to Address for
the Emu 1 at or .
LOADER MACRO DEFINITIONS
FIGURE A-l
8a
b. Instruction Preparation
- For inputting instructions to the Loader three
basic formats are used which correspond roughly to the five
formats used by the AN/UYK-7. The Loader formats are
presented in Figure A - 2 under their respective AN/UYK-7 For-
mat Headings. All fields require a right justified octal
representation. The " i " field should always be either a one
or a zero since it represents a single bit. The combined
" F 3 , K •' field of Format III instructions reguires that K al-
ways be zero? therefore? valia inputs are (0,2,4,6) which
correspond to an F3 of (0,1,2,3). Columns 1-3 must always
be left blank. Columns 15-80 may be used for programmer's
comments. Each instruction is decoded into one 32-bit word
and assigned to the next sequent ial address in memory. How-
ever, if the instruction is a half-word instruction then it
will be stored in the lower half of the previous word if
that word also contained a half-word instruction, else it
will be stored in the upper half of the next sequential ad-
dress. An instruction's sequential address assignment can
only be changed via the "0" or "L" macros, which must pre-
cede the instruction. A sample program is presented in Ap-
pendi x D .
85
FORMAT I
COL
1-3
BLANK
COL
a-5
OPCODE
COL
6
A-REG
COL
7
K
COL
8
B
COL
9
I
COL
10-14
Y-OPERAND
FORMAT II
COL
1-3
BLANK
COL
a-5
OPCODE
COL
6
A-REG
COL
7
F2
COL
8
B
COL
9
I
COL
l o-i a
Y-OPERAND
FORMAT III
COL COL COL COL COL COL COL
1-3 a-5 6 7 8 9 io-ia
BLANK OPCODE A-REG F3,K B I Y-OPERAND
FORMAT IV-A
COL
COL
COL
COL
COL
COL
1-3
a-5
6
7
8
9
BLANK
OPCODE
A-REG
Fa
B
i
FORMAT IV-B
COL COL COL
1-3 a-5 6
BLANK OPCODE A-REG
COL
7-9
SHIFT DESIGNATOR
INSTRUCTION FORMATTING
FIGURE A-2
86
C. TRANSLANG
Several modifications have been made to the D -
Machine and the microprogramming 1 a n g u a a e , TRANSLANG, since
the publication of reference 9 in 1970. Unfortunately, an
addendum to reference 9 has not been published and these
powerful modifications remain undocumented. Because the au-
thors took advantage of these capabilities in writing this
Emulation the changes are documented here to provide 'the
user a ready reference. They include: additional logical
operators, program address modifiers, and an additional Y-
select input register ( B M A R ) .
(1) Logic Ooerators. The additional logic
operators are listed in Table A-l along with the code gen-
erated by the Mi c rot rans 1 at or when they are encounterea. In
the Table, Al and B are assumea as the X/Y input operands
respectively. In addition, listed under the columns la-
belled TRUE/FALSE, are the tests generated by the Micro-
translator when a TRUE/FALSE conditional test is encountered
subseguent to the logical operation.
87
OP MEANING
LSS Less Than
LEQ Less Than or Equal
EGL Equal
NEQ Not Equal
GEO Greater Than or
Equal To
GTR Greater Than
CODE
TRUE
FALSE
GENERATED
TEST
TEST
Al-B
NOT AOV
AOV
1 Al-B-1
NOT AOV
AOV
Al EQV
B
ABT
NOT ABT
Al EQV
B
NOT ABT
ABT
Al-B
AOV
NOT AOV
Al-B-1
AOV
NOT AOV
LOGICAL OPERATORS
TABLE A-l
The programmer is cautioned that when the
Mi c rot rans 1 a t or encounters the keywords TRUE/FALSE it back-
tracks to the last logical operator to determine which test
to generate. Thus a TRUE/FALSE conditional test which is
arrived at through branching may not have generated the ex-
act code the programmer anticipated. These operators were
intended to be used in a seguential fashion as follows:
Al GTR B
If TRUE Then (operation)
The M i c rot pans 1 a t or generates:
Al-B-1
If AOV Then (operation)
The following illustrates circumstances in
which the M i c rot rans 1 a t o r does not generate the code expect-
ed by the programmer:
Al LSS B
If LCI Then Al GTR B;Step Else Skip
If TRUE Then (operation)
88
Generates the code:
Al-B
If LCI Then Al-B-i;Steo Else Skip
If AOV Then (operation)
In this situation "If AOV" is always gen-
erated when the TRUE is encountered? although, obviously if
LCI was not set then the programmer desired to test for
"Less Than".
( 2 ) Program Address Modifiers. Two Dowerful new
instructions were adoed to the D-Machine which allow direct
transfer of orogram control. These are the two Type II in-
structions: "Label -1=MPCR" and "Labe 1 - 1 =CPCR" . The first
causes a direct change in the program sequence by loading
MPCR with the new Label. The second can be classified as a
return jump since it causes a transfer of AMPCR to MPCR/ and
MPCR+1 to AMPCR; thereby setting ud a orogram jump to a
subroutine* and saving the return address. This coae is
i dent i ca 1 to:
Label-1=AMPCR
CALL
The only difference between them is that the CPCR requires
only one instruction for execution, while the CALL requires
two i ns t rue t i ons .
(3) BMAR. The BMAR register is formed by the
concatenation of BR1 or BR2 (16 bits) ana MAR (8 bits). It
can be used as a Y-Input of 24 bits to the Adder. The actu-
al BR register selected is the one most recently referenced
89
in an external operation. The user is cautioned in the use
of BMAR because of its odd size of 24 bits. The unwary pro-
grammer could unintentionally allow extraneous bits in the
most significant byte when BMAR is used for temporary
storage of 16-bit addresses. That is* the assignment
MA1=MAR" is considered to effect a transfer of 16 bits,
while in fact 24 bits are transferred. A subsequent state-
ment of "BMAR=A1" could permit extraneous bits to be intro-
duced in the third least significant byte, if the programmer
had made the assumption that only 16 bits were involved and
automatic masking had taken place. The programmer can force
selection of BR1 or BR2 bv issuing an ASR or ASE, respec-
tively, prior to a BMAR reference. These are considered
external function NOOPS in the Naval Postgraduate School
Configuration; however, they may not appear concurrently
with a BEX statement.
The remainder of the TRANSLANG statements
are reasonably straightforward once the programmer under-
stands the instruction timing idiosyncracies. Reference 9
provides excellent guidance for the novice m i c roproqrammer .
90
APPENDIX B. EMULATOR PROGRAM LISTING
This aopendix provides a copy of the Mi c rot rans 1 a t or
output listing of the Emulator. A copy of the source program
is maintained on cards and also on the Burrough's D-Machine
disk. The object module produced by the M i c rot rans 1 at or is
maintained on disk. Each line of the program is divided
into four sections. The leftmost grouping consists of the
hexadecimal address to which the microinstruction was as-
signed by the Microtranslator during assembly. This is fol-
lowed by the 56-bit microinstruction which was generated.
The middle grouD consists of the programmers' source coding
which was input to the Microtranslator. The rightmost group
consists of the sequence numbers which were assigned to each
input card as it was inserted into the source file on the
disk by the Interpreter's resident 1 i ne-ed i t t i ng proaram
(CARD-LIST) .
91
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ooooooooooooooooooooocoocj
ooooooocooooooooooooooooc
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"gogcgggggggowogggggogggggggggggggggggggggogggggggggggggg
gococoooocogogoggogggocoggocggg
ooooooooooooo
goo
o a o o o ©
G 1 o
w u w
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_ _: LL!
O uj
v a:
a uj
UJ LL
u. u. tt
U. 3 l-
3 CO 05
CD Z
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u ik uj
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138
APPENDIX C. LOADER PROGRAM LISTING
This appendix provides a cooy of the Mi c rot pans 1 at or
output listing of the Loader written in conjunction with the
Emulator. Its source is maintained on disk and cards; and
its object module is maintained on disk. The Loader actual-
ly consists of three separate programs which provide assem-
bly/ debugging and IOC functions to the Emulator. It is a
by-product of the Emulation, and it was used for implementa-
tion and testing of the Emulator. Its functions should be
incorporated in the Emulator Program in the course of expan-
sion to a full emulation.
139
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153
APPENDIX D. SAMPLE AN/UYK-7 SORT PROGRAM
This appendix provides a copy of a sample program which
was used to demonstrate the capability of the D- Machine to
function as an AN/UYK-7. The program, written in AN/UYK-7
Machine Language* will read twelve numbers per card, print
the numbers, sort the input and orint the sorted results.
Any number of cards could be read and sorted until the "END"
card is encountered. At this point the program would reini-
tialize memory and be ready to accept the next program.
Several of the Loader's macro functions, including the L, W ,
D and N options, were utilized along with the appropriate
formats for the five instruction types. It must be em-
phasized that when this program was run the ALGOL Machine
had been removed and the D-Machine reconfigured through mi-
croprogramming to be an AN/UYK-7. The entire output format
and program execution were produced by the Loader/Emulator
combination with the IOP being used strictly as an
Input/Output Channel. Examples of the Loader and Debugaer
output optional listings for this sample program are
presented in Appendix E and F.
15a
ORIGIN
10
SORT ROUTINE AT LOCATION 0002
JUMP TO TITLE ENDING ROUTINE
BEGIN TITLE PRINTING ROUTINE AT
L 00002
D 01001
203320001001
1 10310001002
440310001002
532220000014
523220000003
102320001000
512420000021
320020001000
201320000777
514020000002
101310001002
241310001001
240310001002
330020001000
514020000006
201320001000
530000004040
0 04000
071400005000
071400005352
071400005352
070400001022
071400005044
071400005352
0 7 1400005110
071400005352
071400005154
070410001002
106320001002
446320005416
531220004060
071400005352
071400005220
071400005352
071400005352
071410001002
510000000002 JUMP
0 04040 RETURN HERE
071400005352
071400005352
071400005264
071400005352
071400005330
071400005352
071400005352
071420001002
071400005352
071400005352
51000000401 1
0 04060 START COMPLETION ROUTINES HERE
071400005352
071400001002 PRINT END
7706000 TERMINATE
04000
JUMP TO COMPLETION ROUTINE IF END CARD
TO BEGINNING OF SORT ROUTINE
FROM SORT ROUTINE AND FINISH TITLES
PROGRAM AND RESTART EMULATOR
155
Iff 05000
M 05022
W 050U4
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123 a56 789 987 65a 321 023 a56 875 888 555 213
357 652 389 123 583 7a2 928 65a 987 2a8 965 281
321 to5a 987 123 a56 789 369 258 147 963 852 7ai
END TERMINATE SORT ROUTINE/ READY FOR NEXT PROGRAM
AN/UYK-7 EMULATION DEMONSTRATION PROGRAM
THIS IS A TEST OF THE AN/UYK-7 EMULATION
USING A MAChlNE LANGUAGE PROGRAM
FOR A DEMONSTRATION SORT ROUTINE USING
THE FOLLOWING INPUT NUMBERS:
THE RESULTS OF THIS SORT
ARE AS FOLLOWS:
156
APPENDIX E. SAMPLE LOADER OUTPUT LISTING
This aopendix provides a copy of the output received
from the Loader when the sample program discussed in Appen-
dix D is run. This output is obtained by turning on the IRQ
switch on the Loader's Interpreter. The output serves as a
hard copy program listing for the programmer and can be
utilized for debugging. The address to the left of each in-
struction is the octal assignment for that instruction,
derived from the last "0" or "L" card/ and was offset by
1024. The Loader inout is terminated by an " N" card which
initializes the PAR and signals the Emulator to commence ex-
ecution.
157
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160
APPENDIX F. SAMPLE DEBUGGER OUTPUT LISTING
This appendix provides a sample of the output received
from the Loader when it was used as a debugger for the sam-
ple program discussed in Appendix D. This output is ob-
tained by turning on the IRQ switch on the Emulator's Inter-
preter. The switch was not left set for the entire
program's execution because the output requires approximate-
ly thirty pages. The IRQ switch causes all C M R registers
from address 0000 to 0035 to be printed as each instruction
is executed. Each time and instruction does a Y-Operand
write that address is also dumped. The addresses are print-
ed in the leftmost column and include the following informa-
tion which can be used during program debugging:
OCTAL
ADDRESS
0-7
10
11-17
20-27
30
31
32
33
3a
35
DESCRIPTION
Task A-Register contents
Unused (always = 0)
Task Index B-Register contents
Task Base S-Pegister contents
Repeat Instruction (if applicable)
Current Instruction being
Repeated (if applicable)
Current Indirect Control
Word (if applicable)
Y-Operand for Indirection
( i f appl i cabl e )
ICW address in memory (if applicable)
Program Address Register
Those addresses marked "if applicable" would normally
be zero/ but could contain data if either the Repeat mode or
161
Indirection mode had been used previously in the program.
The lower 20 bits of aodress 0035 (PAR) point to the octal
address of the next instruction. The upper \2 bits of the
PAR are those ASR bits which were implemented as discussed
in Section C of Chapter V. It is noteworthy that the output
is an eleven bit octal representation of a 32-bit binary
word* thus the leftmost octal digit represents only two
bits.
by utilizing this optional listing in combination with
the Loader listing, . the programmer should be capable of
proceeding through his program step by step. This facility
proved an invaluable aid in troubleshooting the Emulator as
each new instruction was written and tested.
162
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16b
GLOSSARY
Active Status Register (ASR): A special word in the AN/UYK-7
used to indicate the status of special conditions or
mooes of operation. Each bit of the word has a
separate meaning to the central processor.
ADO: The Burrough's Advanced Design Organization, Paoli,
Pennsylvania, which designed the Naval Postgraduate
School's D-Machine.
A Registers (Al, A2, A3): Each of the three A registers is
functionally identical. The A registers are used for
temporary data storage within the Logic Unit of the In-
terpreter and serve as a primary input to the adder.
Adder: The adder in the Logic Unit of the Interpreter, is a
modified version of a straightforward carry lookahead
adder. It is also used for executing logic operations.
Alternate Microprogram Count Register (AMPCR): The AMPCR is
a 12-bit register in the Memory Control Unit of. the In-
terpreter, which contains the jump or return address
for program jumps and subroutine returns within a mi-
c roorogram .
AMPCR: Alternate Microprogram Count Reaister.
Arithmetic (A) Registers: There are two sets of eight Arith-
metic Registers in the AN/UYK-7. They are used exten-
sively in arithmetic calculations and are directly ad-
dressable by the programmer.
ASR: The Active Status Word in the AN/UYK-7.
8 Register: The B register is the primary interface between
the Logic Unit of the Interpreter and the Data/Program
Memory or Devices through the Switch Interlock. It
also serves as a secondary inDut to the adder.
167
Barrel Switch: The barrel switch is a matrix of gates in the
Logic Unit of the Interpreter, used to shift a parallel
data word any number of places to the left or right in
a si ngl e c 1 ock t i me.
Base Registers 1 and 2 (BR1, BR2): The Base Registers are
two 8-bit registers in the Memory Control Unit of the
Interpreter/ which usually contain the base address of
a 256-word block of Data/Program Memory.
Base (S) Registers: There are two sets of eight Base Regis-
ters in the AN/UYK-7 used extensively in multi-
programming and mul t i -process i ng. Base registers are
used for operand address calculations.
8R1 and BR2: Base Registers 1 and 2 in the Interpreter.
Building Block: The term used to describe the primary tunc
tional units of the Interpreter Based System and in'
eludes: Interpreter, Data/Program Memory and Switch In'
t er 1 oc k .
Control Memory Registers (CMR): A block of 89 registers in
the AN/UYK-7 usea for SDecial fast memory operations.
Condition Register (COND): The COND is a 12-bit register in
the Control Unit of the Interpreter and is used to
store various condition bits for use during program ex-
ecution.
Central Processing Unit (CPU): The primary arithmetic and
control unit in a conventional computer system.
Condition Select: The condition select is a matrix of gates
in the Control Unit of the Interpreter that computes
the results of a computation or logic operation in the
Logic Unit with a preselected result. The results of
the comoarison may be used to determine the sequence of
execution of microprogram instructions.
Control Unit (CU): The CU, one of the five functional units
of the Interpreter, is used for condition testing and
the storage and aistribution of enable signals received
from the nano i ns t rue t i ons .
168
Counter (CTR): The CTR is an 8-bit counter in the Z register
section of the Memory Control Unit of the Interpreter,
used for loop control and other counting functions.
CTR: Counter in the Interoreter.
Data/Program Memory: The Data/Program Memory of the Inter-
preter, also called S-Memory, provides storage for data
and program, and functions similarly to the main memory
modules of a conventional computer system.
Emulation: Describes a process through which the hardware
components of one machine (Host) are made to "appear"
to assume the specific characteristics of the hardware
of another machine (target).
End-Around-Sh i f t : A shift operation in either the left or
right direction, in which the bit or bits which would
be shifted out of the register are reinserted in the
more significant end.
End-Of f -Sh i f t : A shift ODeration in either the left or right
direction, in which the bit or bits shifted out of the
register are lost. Vacated bit dosi t ions are automati-
cally replaced by zeros.
Firmware: In the Interoreter Based System, firmware is the
combination of stored logic in the micro-memory and the
hardware logic of the Interpreter.
GC Bits: A set of two (GC1, GC2) global condition bits in
the Interpreter. They are used as lockouts during com-
munications to the I/O processor.
HALFFETCH: A subroutine written for the Emulator, which is
executed when a halfword instruction has been decoded.
Horizontal: A tyoe of microprogramming instuction which con-
trols multiple gates simultaneously allowing parallel
functions to execute.
Host: A term used in Emulation to define the machine on
which another machine is to be emulated (imitated). In
this thesis the Burrough's D-Machine.
169
ICw: Indirect Control Word in the AN/UYK-7.
IFE1CH: A subroutine written for the Emulator, which reads
the next instruction from main memory, deciphers the
Op-code and passes control to the appropriate Op-code
execution subroutine.
Incrementer (INCR): The INCR is in the Memory Control Unit
of the Interpreter and increments the address of the
next microinstruction to be executed by the Interpreter
by zero, one or two, depending on the successor in-
struction which is either implied or specified. A WAIT
causes an increment by zero, a STEP causes an increment
by one, and a RETN causes an increment by two.
Indirection: An addressing technigue or mode of operation of
the AN/UYK-7 in which Y-Ooerand address calculation
points to an Indirect Control Word (ICW) which in turn
points to the ooerand or another ICW. Indirection is
determined by the i-field of an instruction.
Indirect Control rtord (ICW): The ICW is a 32-bit word in the
AN/UYK-7 used in Indirection which can be broken down
into several fields. The fields determine the mode of
indirect address calculation to be used in pointing to
the next ICW or the Y-ODerand.
Indexing: An addressing technique wherein the normal address
calculated is incremented/decremented (indexed) by the
value in the specified index register.
Index (B) Register: There are two sets of seven Index Regis-
ters in the AN/UYK-7. They provide the ability to per-
form Indexing during memory referencing, and may also
be used as counters.
INT: An Interrupt signal issued by an Interpreter.
Interpreter: The Interpreter is the basic building block of
the Interpreter-Based System. Functionally, it is
characterized by the combination of microprogram in-
structions stored in its M memory and the combination
of bits in its nano i nst rue t i on which enable signals to
implement the hardware logic.
170
Interpret er-9aseci System: A computer design concept that
provides, in the form of basic building blocks, the
throughput and flexibility for a variety of data pro-
cessing requirements.
Interrupt: In the AN/UYK-7, the Interrupt signals the cen-
tral processor to cease its normal instruction flow and
respond to a request for services. In the D- Machine,
Interrupt (INT) is a flag which may oe set between pro-
cessors siqnallinq that a message has been placed in
the Mailbox.
Least Significant Bit (LS8): For a number or value
represented in binary notation, that bit position which
represents the least significant portion of the number.
LIT: Literal Register in the Interpreter.
Literal Reaister (LIT): An 8-bit register in the Z section
of the Memory Control Unit of the Interpreter, which is
used for temporary storage of literals from microin-
st rue t i ons .
Logic Unit (LU): The LU is one of the five major functional
units of the Interpreter. It performs all of the ar-
tihmetic, Boolean logic, and shifting operations of the
Interpreter.
Mailbox: An address (64K) in the In t eroret er ' s S-Memory
which is used for passing messages between Interpreters
and the IOP.
MAR: Memory Address Register in the Interpreter.
Memory Address Register (MAR): The MAR is an 8-bit register
in the Memory Control Unit of the Interpreter, which
contains the least significant 8 bits of a memory or
device address.
Memory Control Unit (MCU): The MCU is one of the five major
functional units of the Interpreter. It controls the
sequence of execution for microinstructions; the ad-
dressing of Data/Program Memory; and the selection of
aev ices.
171
Memory Information Register (MIR): Th^ MIR is a register in
the Loaic Unit of the Interpreter which serves as the
output interface register between the Interpreter and
the Switch Interlock.
Microprogram Address Control Register (MPAD CNTL): The MPAD
CNTL, a register in the Memory Control Unit of the In-
terpreter - controls the loading of the MPCR and the
AMPCR, and determines the value of the increment.
Microprogram Count Register (MPCR): The MPCR, located in the
Memory Control Unit of the Interpreter, is a 12-bit re-
gister that usually contains the address, in M-memory,
of the microinstruction presently being executed by the
Interpreter.
Microproaram Memory ( M -Memory): The M -Memory is one of the
five major functional units of the Interpreter. It
stores microinstructions which characterize the Inter-
preter for a given apDlication, and may be implemented
as a read/ write semiconductor memory.
Microprogramming: A technique for implementing the control
functions of a digital computer using programmable con-
trol signals in a separate memory called a control
store, which is organized on a word basis.
MIR: Memory Information Reaister in the Interpreter.
Monoorogramming: A general computer operating environment in
which one program at a time is executed.
Most Significant Bit (MSB): For a number or value represent-
ed in binary notation, that bit position which
represents the most significant portion of the number,
or the sign of the number.
MPCR: The Microprogram Count Register in the Interpreter.
Multiprogramming: A general computer operating environment
in which more than one program at a time is executed
with each given a fixed time slice.
172
Multiprocessing: A general comouter operating environment in
which two or more central processors execute simultane-
ously* and share resources; such as, memory and I/O
dev ices.
Multiprocessor: A network of computers capable of simultane-
ously executing two or more programs or sequences of
instructions by means of multiprogramming, parallel
processing or both.
Nanoi nst rue t i on : A single instruction stored in N-Memory of
the Interpreter, the contents of which constitue 56
unique signals for controlling hardware loqic of the
Interpreter.
Nanomemory (N-Memory): The N-Memory, one of the five func-
tional units of the Interpreter, stores 56 specific en-
able signals for the hardware loqic within the Logic
Unit, Control Unit, and Memory Control Unit.
Page:
« grouping of addresses of fixed length. In the Emu-
lator the AN/UYK-7 memory was treated as eight pages of
8K each .
PAR: Program Address Register in the AN/UYK-7.
Program Address Register (PAR): A register in the AN/UYK-7
which holds the address of the next instruction to be
accessed.
Port Select Unit (PSU): The PSU orovides control and the
electrical interface between a single Interpreter and
its Devices and Data/Program Memory.
Shift Amount Register (SAR): The SAR is a 6-bit register in
the Control Unit of the Interpreter and is used to
store the number of positions a word or literal is to
be shifted by the barrel switch.
Switch Interlock (SirtI): The S W I provides the interconnection
between Interpreters, Data/Program Memory, and Devices
of an Interpreter Based System. Its function is to
permit any one of a multiolicity of Interoreters to ac-
cess all modules of an array of Data/Program Memory
and/or all Devices.
173
Target: A term used in Emulation to define a machine to be
emulated (imitated). In this thesis, the AN/UYK-7.
TRAN SLANG: A computer programming language designed to con-
vert oseudo-Eng 1 i sh language statements defining the
action of the Interpreter for each machine cycle into
binary patterns for the M - Memories.
Vertical: A mi c roorogrammi ng instruction which controls
those gates needed for a single function execution.
Z Register Section: A collection of registers and selection
gates in the Memory Control Unit of the Interpreter,
which includes the CTR, LIT, and Input Selection gates
used to control the execution sequence of m i c roi ns t rue-
t i ons .
17a
BIBLIOGRAPHY
1. A g r a w a 1 a , A. K. and R a u s h e r , T. G . , "Microprogramming:
Perspective and Status," IEEE Trans, C23, p. 817-37,
August 197a.
2. Allred, G. R., "System/370 Integrated Emulation Under OS
and DOS," Proceedings SJCC, 38, p. 163-67, 1971.
3. Almes, G. T., Drongowski, P. J., and Fuller, S. H.,
"tmulating the Nova on the POP 11/40: A Case Study,"
Computer Conference, p. 53-6, Fall 1975.
4 . Bagley, J. D., "Microprogrammable Virtual Machines,"
Computer, p. 38-42, February 1976.
5. Boulaye, G. and Mermet, J., Microprogramming, Herman,
Paris, 1972.
Briefer, G. 8., "Taking the Risk Out of System Upgrad-
ing," Data Processinq Magazine, 12, d. 27-9, Sep-
tember 1970.
Burrouah's Corporation Report 64116, Emulation Facility,
by Advanced Design Organization, Paoli, Pa., 28 June
1971.
8. Burrough's Corporation Report TR70-2, The Interpreter,
by R. L. Davis, 16 February 1970.
9. Burrough's Corporation Report TR70-8, Microprogramming
Manual for Interpreter Based Systems, by Advanced
Design Organization, Paoli, Pa., November 1970.
10. Burrough's Corporation Report 66143, Algol Reference
Manual for the Interpreter Based System, by Advanced
Design Organization, Paoli, Pa., 15 June 1975.
175
11. Dolhoff, T. L., "The Negative Aspects of Microprogram-
ming," Datamation, 20, p. 64-6, July 1974.
12. E 1 1 e n b y , J., "Emulation and Competition in I/O System
Design," Computer Conference, o. 303-6, 1974.
13. Flynn, M. J., Neuhauser, C, and McClure, R. M., "EMMY-
An Emulation System for User Microprogramming,"
Proceedings NCC, 44, p. 85-9, 1975.
14. Galey, J. M., "Microprogramming: The Bridge Between
Hardware and Software," Computer, p. 23, August
1975.
15. Husson, S. S., Mi c roDroarammi ng Principles and Prac-
tices, Prentice-Hall, Inc., 1970.
16. Jaeger, R., "Microprogramming: A General Design Tool,"
Computer Design, 13, o. 150-7, August 1974.
17. Jones, L. H., "Instruction Sequencing in Microprogrammed
Computers," Proceedings NCC, 44, p. 91-8, 1975.
18. Jones, L., "A Survey of Current work in Microprogram-
ming," Computer, p. 33-8, August 1975.
19. Jones, L. H. and Merwin, R. E., "Trends in Microprogram-
ming. A Second Reading," IEEE Trans, C23, p. 754-9,
August 1974.
20. Kahn, P. G. and Fuller, M. E., "Proaram Conversion: A
Discussion of Techniques, " Data Processing Magazine,
11, p. 28-31, November 1969.
21. Mallach, E. G., "Emulator Architecture," Computer, p.
24-32, August 1975.
176
22. Mandell, R. L., "Hardware/Software Trade-Offs — Reasons
and Directions," Proceedinas FJCC, 41, o. 453-9,
1972.
23. Rauscher, T. G., "On the Feasibility of Emulating the
AN/UYK-7 Computer on the AAOC Signal Processing Ele-
ment/" NTIS, November 1972.
24. Reigel, E. W. V. and Fisher D. A., "The In t erpret er--A
Mi c poprogrammab 1 e Building Block System," Proceed-
ings SJCC, ao, p. 705-23, 1972.
25. Rosin, R. F., "Contemporay Concepts of Microprogramming
and Emulation," Computer Survey, 1, p. 197-212, De-
cember 1969.
26. Sperry Rand, UNIVAC, ComDuter Set AN/UYK-7 (V) Technical
Manual Volume 1, Navships 0967-319-40 1 0 , January
1971.
27. Sperry Rand, UNIVAC, AN/UYK-7, Technical Description.
28. Tucker, A. B. and Flynn, M. J., "Dynamic Microprogram'
ming: Processor Organization and Programming," Com'
munications of the ACM, 14, p. 240-50, April 1971.
29. Wilkes, M. B. "The Growth of Interest in Microprogram'
ming: A Literature Survey," Computer Survey, 1, p
139-45, September 1969.
177
INITIAL DISTRIBUTION
1. Defense Document at i on Center
Cameron Station
Alexandria/ Virginia, 22314
No. Copi es
2
2. Library, Code 0212
Naval Postgraduate School
Monterey, California 93940
3. Department Chairman, Code 52
Computer Science Group
Naval Postgraduate School
Monterey, California 93940
4. Professor S. Jauregui, Code 62JA
(Thesis Adv isor)
Department of Electrical Engineering
Naval Postgraduate School
Monterey, California 93940
5. LT. Lyle V. Rich, Code 52RS
(Second Reader)
Department of Computer Science
Naval Postgraduate School
Monterey, California 93940
6. Mr . J . Lynch
Bur rough ' s ADO
Federal and Special Systems Group
P.O. BOX 517
Paoli, Pa. 19301
7 . Mr Carl Benson
Naval Electronics Systems Engineering Center
P. 0. Box 80337
San Diego, California 92138
178
8. Mr. J. Lopata
Burrough's Corporation
P. 0. Box 517
Paoli, Pa. 19301
9. Lt. Jerry M. Haggerty
103 Moran Circle
Monterey, California 93940
10. Lt. John M. Hartling
376 A . Bergi n Drive
Monterey/ California 93940
11. Naval Electronics Systems Command
Code PME 107
Washington, D. C. 20360
Attn: CAPT W. Flowers
12. Naval Electronics Systems Command
Code PME 107
Washington, D. C. 20360
Attn: Mr. R. Matterazza
13. Naval Electronics Systems Command
Code PME 107
Washington, D. C. 20360
Attn: CAPT H. Leavitt
179
Thesis
168148
H1116
Haggerty
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Emu 1 at
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Emulati
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DUDLEY KNOX LIBRARY
3 2768 00353584 0